M58BW16FB4T3F NUMONYX, M58BW16FB4T3F Datasheet - Page 22

• Manufacturer Part Number: M58BW16FB4T3F
• Description: IC FLASH 16MBIT 45NS 80PQFP
• Manufacturer: NUMONYX

Specifications of M58BW16FB4T3F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (512K x 32)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M58BW16FB4T3FCT

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Latch Enable (L)
The Bus Interface can be configured to latch the Address inputs on the rising edge of Latch
Enable, L, for Asynchronous Latch Enable Controlled Read or Write or Synchronous Burst
Read operations. In Synchronous Burst Read operations the address is latched on the
active edge of the Clock when Latch Enable is Low, V
change without affecting the address used by the memory. When Latch Enable is Low, V
the latch is transparent. Latch Enable, L, can remain at V
and Write operations.
Burst Clock (K)
The Burst Clock, K, is used to synchronize the memory with the external bus during
Synchronous Burst Read operations. Bus signals are latched on the active edge of the
Clock. In Synchronous Burst Read mode the address is latched on the first rising clock edge
when Latch Enable is Low, V
During Asynchronous Bus Operations the Clock is not used.
Burst Address Advance (B)
The Burst Address Advance, B, controls the advancing of the address by the internal
address counter during Synchronous Burst Read operations.
Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the
X-latency time has expired. If Burst Address Advance is Low, V
counter advances. If Burst Address Advance is High, V
not change; the same data remains on the Data inputs/outputs and Burst Address Advance
is not sampled until the Y-latency expires.
The Burst Address Advance, B, may be tied to V
Valid Data Ready (R)
The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to
identify if the memory is ready to output data or not. The Valid Data Ready output can be
configured to be active on the clock edge of the invalid data read cycle or one cycle before.
Valid Data Ready, at V
Ready is Low, V
Write Protect (WP)
The Write Protect, WP, provides protection against Program or Erase operations. When
Write Protect, WP, is at V
Protection Configuration Register is activated. Program and Erase operations to protected
blocks are disabled. When Write Protect WP is at V
erased, if no other protection is used.
IL
, the previous data outputs remain active.
IH
, indicates that new data is or will be available. When Valid Data
IL
, the protection status that has been configured in the Block
IL
, or on the rising edge of Latch Enable, whichever occurs first.
IL
.
IH
IL
all the blocks can be programmed or
IH
. Once latched, the addresses may
IL
, the internal address counter does
for Asynchronous Random Read
IL
, the internal address
IL
,