RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 43

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

10.3.3
10.3.4
Datasheet
Figure 21. Example Latency Count Setting
Figure 22. Data Hold Timing
A[MAX:0]
D[15:0]
ADV#
Figure 21
WAIT Polarity
The WAIT Polarity (WP) bit selects the asserted, or true, state of WAIT. When WP is set, WAIT is
an active-high signal (default). When WP is cleared, WAIT is an active-low signal.
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid
on D[15:0] for one or two clock cycles. When DH is set, output data is held for two clocks
(default). When DH is cleared, output data is held for one clock cycle. (See
processor’s data setup time and the flash memory’s clock-to-data output delay should be
considered in determining whether to hold output data for one or two clocks.
CLK
CE#
Data Hold
Data Hold
1 CLK
2 CLK
shows an example of a LC setting of Code 3.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
DQ
DQ
0
15-0
15-0
CLK [C]
Code 3
[D/Q]
[D/Q]
1
High-Z
R103
Address
Output
Valid
2
Output
Valid
Output
Valid
3
t
Data
Output
Data
Figure
Valid
Output
4
Valid
22.) The
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