RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 63

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

Datasheet
BEFP (busy)
BEFP Exit
(Busy)
BEFP Exit
Write to Buffer
setup
Count Load
Data Load
Write to Buffer
Confirm
Write to Buffer
setup Ers. Susp.
Count Load Ers.
Susp.
Data Load Ers.
Susp.
Write to Buffer
confirm Ers.
Susp.
Erase Setup
Erase (busy)
Read Status Ers.
Susp.
Read Array Ers.
Susp.
Read Config
Ers. Susp.
Read Query Ers.
Susp.
Erase (done)
STS Reconfig
Setup
STS Reconfig
Setup Ers. Susp.
STS Reconfig
Setup Prog.
Susp.
STS Reconfig
Setup Both
Susp.
NOTES:
1. For BEFP, the block address should be changed only when the buffer is full.
2. Start address is the address loaded during the Count Load cycle.
3. The Write to Buffer command is invalid when a botch has occurred. The status register should be cleared before issuing the Write to Buffer command.
4. A Clear Status Register command is allowed during erase or program suspend.
5. When a suspend command is issued while the device is busy (program or erase), the device will not enter suspend until the appropriate suspend latency has elapsed.
6. When the lock/write RCR operation is complete, the device returns to Read Status mode. If the Lock Setup command is issued during Erase Suspend, the device will
7. The Confirm command (0xD0) is interpreted as the second cycle of a two-cycle command while a Resume command 0xD0 is interpreted as a stand-alone, single-cycle
8. Both Suspend indicates a Program Suspend nested within an Erase Suspend.
9. A Botch state is indicated when status bits SR4 and SR5 are set, and is the result of an invalid command sequence. The Clear Status Register command (0x50)must
Current State
Table 25. Next State Table Part B
Any additional commands issued during this latency interval will cause indeterminate results.
revert to Read Status Ers. Susp.
command. The device will not resume from suspend when the command sequence 0x20, 0xD0 is issued while in suspend state.
be issued to continue.
SR7
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
SR0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
z
When
Read
Data
Config
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Array
CFI
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Data load; To quit or abort, change the block address during a write. The UI will botch on a block change. Repeat Data Load until Word Count
Data load; To quit or abort, change the block address during a write. The UI will botch on a block change. Repeat Data Load until Word Count
Read Status
Read Status
Read Status
Read Status
Read Status
Read Status
If second cycle is 0x00 or 0x01 or 0x02 or 0x03, then reconfigure the STS functionality and go to Read Status Prog.Susp; If not Botch Prog.
Word count load (Actual number of words-1). Lowest five bits will be assumed as the count. Device assumes next cycles will be Data Load.
Word count load (Actual number of words-1). Lowest five bits will be assumed as the count. Device assumes next cycles will be Data Load
If second cycle is 0x00 or 0x01 or 0x02 or 0x03, then reconfigure the STS functionality and go to Read Status Both Susp; If not Botch Both
Status
Ers. Susp.
Ers. Susp.
Ers. Susp.
Ers. Susp.
If second cycle is 0x00 or 0x01 or 0x02 or 0x03, then reconfigure the STS functionality and go to Read Status Ers. Susp; If not Botch Ers.
Read
0x70
If second cycle is 0x00 or 0x01 or 0x02 or 0x03, then reconfigure the STS functionality and go to Read Status; If not Botch.
Read Array Ers.
Read Array Ers.
Read Array Ers.
Read Array Ers.
Status
Read Array
Read Array
Clear
0x50
Susp.
Susp.
Susp.
Susp.
Repeat command until SR7=1. Next cycle will be interpreted as Count Load Ers. Susp..
Internally timed; Go to BEFP Exit after internal timeout; Transition indicated by SR0=0
4
Repeat command until SR7=1. Next cycle will be interpreted as Count Load.
To exit, change block addr; to continue proceed to BEFP after SR0=0.
is reached, next command must be Write to Buffer Confirm Ers. Susp.
Read Config
Read Config
Read Config
Read Config
Read Config
Read Config
Config
Ers. Susp.
Ers. Susp.
Ers. Susp.
Ers. Susp.
Read
0x90
is reached, next command must be Write to Buffer Confirm
Command Input and Next State
Botch Ers. Susp. (command sequence error)
STS Reconfig
STS Reconfig
STS Reconfig
STS Reconfig
STS Reconfig
STS Reconfig
STS Re-
Botch (command sequence error)
Botch (command sequence error)
config
Setup Ers.
Setup Ers.
Setup Ers.
Setup Ers.
0xB8
Setup
Susp.
Susp.
Susp.
Susp.
Setup
Erase (busy)
Ers. Susp..
Susp.
Susp.
Susp.
Read Query
Read Query
Read Query
Read Query
Read Query
Read Query
Query
Ers. Susp.
Ers. Susp.
Ers. Susp.
Ers. Susp.
Read
0x98
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Setup
Ers. Susp.
Ers. Susp.
Ers. Susp.
Ers. Susp.
Lock
0x60
Prot. Prog. Setup
Prot. Prog. Setup
Read Array Ers.
Read Array Ers.
Read Array Ers.
Read Array Ers.
OTP/Prot
Program
Setup
0xC0
Susp.
Susp.
Susp.
Susp.
Commands
Read Array Ers.
Read Array Ers.
Read Array Ers.
Read Array Ers.
Read Array
Read Array
Illegal
Susp.
Susp.
Susp.
Susp.
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