ISL9206DRZ-T Intersil, ISL9206DRZ-T Datasheet
ISL9206DRZ-T
Specifications of ISL9206DRZ-T
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ISL9206DRZ-T Summary of contents
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... MARKING RANGE (°C) ISL9206DHZ-T 206Z -20 to +85 ISL9206DRZ-T 06Z -20 to +85 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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Absolute Maximum Ratings (Reference to GND) Supply Voltage (VDD ...
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Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: T PARAMETER Device Wake-Up Time Device Sleep Wait Time Auto-Sleep Time-Out Period OTP ROM Write Time Hash Calculation ...
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Typical Applications PACK+ XSD PACK- FIGURE 1. TYPICAL APPLICATION WITH THE ISL9206 POWERED BY THE BATTERY PACK+ XSD PACK- FIGURE 2. TYPICAL APPLICATION WITH THE ISL9206 POWERED BY THE XSD BUS Block Diagram VDD XSD VSS 4 ISL9206 R 2 ...
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Theory of Operation The ISL9206 contains all circuitry required to support battery pack authentication based on a challenge-response scheme. It provides a 16-Byte One-Time Programmable Read-Only Memory (OTPROM) space for the storage 96-Bit of secret for the ...
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OTP ROM The 16-Byte OTP ROM memory is based on EEPROM technology and is incorporated into the ISL9206 for storage of non-volatile information. OTP ROM contents (refer to Table 8) can include but not limited to: 1) Device default settings ...
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FIGURE 5. AUTHENTICATION PROCESS FLOW DIAGRAM It is recommended that device authentication be done once in a while to maximize its effectiveness. Before a new challenge code can be accepted by the device, the SESL register must be re-written again ...
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... XSD Host Bus Interface Communication with the host is achieved through XSD, a light-weight subset of Intersil’s ISD single-wire bus interface. XSD is a programmable-rate pseudo-synchronous bidirectional host-initiated instruction-based serial communication interface that allows up to two slave devices to be attached and addressed separately. It includes features to enable quick and reliable communication ...
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HOST Open-Drain Port Pin TX RX FIGURE 7. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS XSD TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING PARAMETER SYM Bit Time 0. ...
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BYTES BYTES BYTES FIGURE 9. THE 16-BIT INSTRUCTION FRAME FIELD DEFINITION OPCODE DESCRIPTION 00 Write Operation 01 Read Operation (normal) 10 Read Operation (with CRC) Read from device register. Append 1-Byte CRC to the end of the ...
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Bus Transaction Protocol The XSD bus for the ISL9206 defines three types of bus transactions. Figure 10 shows the bus transaction protocol. The blue color represents the signal sent by the host and the green color stands for the signal ...
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... These registers are used during the battery pack authentication process. Table 10 describes the mapping of the Authentication registers. Bank 3 is reserved for Intersil production testing only, and will not be accessible during normal operation. Accessing the Test and Trim Registers when not in test mode will result in a bus error ...
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TABLE 9. CONTROL AND STATUS REGISTERS (BANK 1) ADDRESS NAME DESCRIPTION 1-00 MSCR Master Control 1-01 STAT Device Status ADDRESS NAME DESCRIPTION 2-00 SESL Secrets Selection 2-01 CHLG Challenge Code Register 2-05 AUTH Authentication Code Register TABLE 11. DEFAULT CONFIGURATION ...
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ADDRESS 0-06/07/08/09: AUTHENTICATION SECRET SET #2 (SE2A/B/C/D) These address locations store the second set of secrets to be used for hash calculation. Reading and writing to this register can be disabled by setting the SLO[1] bit at OTP ROM location ...
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... One way is to use a spare UART (Universal Asynchronous Receiver/Transmitter). A GPIO (general purpose input/output) can be used if no UART is available for the XSD communication. Refer to application note AN1167 available from Intersil for more information regarding how to implement the XSD bus within a microprocessor. Pull Up Resister Selection ...
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Small Outline Transistor Plastic Packages (SOT23- 0.20 (0.008 0.10 (0.004 WITH PLATING b1 c BASE METAL ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...