PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 10

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
UJA1076_2
Product data sheet
Fig 4.
SDO
SCS
SCK
SPI timing protocol
SDI
6.2.1 Introduction
6.2.2 Register map
floating
6.2 SPI
X
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave operations. The SPI is configured for full duplex
data transfer, so status information is returned when new control data is shifted in. The
interface also offers a read-only access option, allowing registers to be read back by the
application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge (see
The first three bits (A2, A1 and A0) of the message header define the register address.
The fourth bit (RO) defines the selected register as read/write or read only.
Table 3.
Address bits 15, 14 and 13
000
001
010
011
X
•
•
•
•
sampled
SCSN: SPI chip select; active LOW
SCK: SPI clock; default level is LOW due to low-power concept
SDI: SPI data input
SDO: SPI data output; floating when pin SCSN is HIGH
01
MSB
MSB
Figure
Register map
02
All information provided in this document is subject to legal disclaimers.
4).
14
14
Rev. 02 — 27 May 2010
03
13
13
Write access bit 12 = 0
0 = read/write, 1 = read only
0 = read/write, 1 = read only
0 = read/write, 1 = read only
0 = read/write, 1 = read only
04
12
12
High-speed CAN core system basis chip
15
01
01
Read/Write access bits 11... 0
WD_and_Status register
Mode_Control register
Int_Control register
Int_Status register
16
LSB
LSB
UJA1076
© NXP B.V. 2010. All rights reserved.
floating
mce634
X
10 of 47