PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 13

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
Table 6.
UJA1076_2
Product data sheet
Bit
15:13
12
11
10
9:8
7:6
5:4
3
2
1
Symbol
A2, A1, A0 R
RO
V1UIE
V2UIE
reserved
WIC1
WIC2
STBCC
RTHC
WSE1
Int_Control register
6.2.5 Int_Control register
Access Power-on
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
default
010
0
0
0
00
00
00
0
0
0
All information provided in this document is subject to legal disclaimers.
Description
register address
access status
V1 undervoltage interrupt enable
V2 undervoltage interrupt enable
wake-up interrupt 1 control
wake-up interrupt 2 control
CAN standby control
reset threshold control
WAKE1 sample enable
0: register set to read/write
1: register set to read only
0: V1 undervoltage warning interrupts cannot be requested
1: V1 undervoltage warning interrupts can be requested
0: V2 undervoltage warning interrupts cannot be requested
1: V2 undervoltage warning interrupts can be requested
00: wake-up interrupt 1 disabled
01: wake-up interrupt 1 on rising edge
10: wake-up interrupt 1 on falling edge
11: wake-up interrupt 1 on both edges
00: wake-up interrupt 2 disabled
01: wake-up interrupt 2 on rising edge
10: wake-up interrupt 2 on falling edge
11: wake-up interrupt 2 on both edges
0: When the SBC is in Normal mode (MC = 1x):
When the SBC is in Standby/Sleep mode (MC = 0x):
1: CAN is in Lowpower mode with bus wake-up detection enabled,
regardless of the SBC mode (MC = xx). CAN wake-up interrupts can be
requested.
0: The reset threshold is set to the 90 % V1 undervoltage detection voltage
(V
1: The reset threshold is set to the 70 % V1 undervoltage detection voltage
(V
0: sampling continuously
1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled
by WBC)
CAN is in Active mode. The wake-up flag (visible on RXDC) is cleared
regardless of V2 output voltage.
CAN is in Off mode. Bus wake-up detection is disabled. CAN wake-up
interrupts cannot be requested.
uvd
uvd
Rev. 02 — 27 May 2010
; see
; see
Table
Table
10)
10)
High-speed CAN core system basis chip
UJA1076
© NXP B.V. 2010. All rights reserved.
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