LTC4268IDKD-1#TRPBF Linear Technology, LTC4268IDKD-1#TRPBF Datasheet - Page 41

• Manufacturer Part Number: LTC4268IDKD-1#TRPBF
• Description: IC PD HIGH POWER W/CNTRL 32-DFN
• Manufacturer: Linear Technology
• Type: Power over Ethernet Switch (PoE)r

Specifications of LTC4268IDKD-1#TRPBF

• Applications: Remote Peripherals (Industrial Controls, Cameras, Data Access)
• Internal Switch(s): Yes
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For each secondary-side power MOSFET RMS current is
given by:
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high V
transition power loss term is included for accuracy. C
is the most critical parameter in determining the transition
loss, but is not directly specifi ed on the data sheets.
C
on most MOSFET data sheets (Figure 17).
The fl at portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops.
The Miller capacitance is computed as:
The curve is done for a given V
for different V
computed C
the curve specifi ed V
With C
MOSFET power dissipation:
where:
APPLICATIONS INFORMATION
MILLER
R
V
f
V
I
P
C
V
OSC
RMS(SEC)
TH
D(PRI)
GATE(MAX)
DR
MILLER
IN(MAX)
MILLER
is the MOSFET gate threshold voltage
is the gate driver resistance (≈10Ω)
is the operating frequency
is calculated from the gate charge curve included
=I
=
•
MILLER
RMS(PRI)
=
determined, calculate the primary-side power
P
DS
Q
= 7.5V for this part
DC
IN(MAX)
B
V
voltages are estimated by multiplying the
1− DC
− Q
MIN
DS
I
by the ratio of the application V
OUT
2
A
DS
• R
• R
MAX
.
DS(ON)
DR
•
V
DS
GATE(MAX)
(
1+ δ
. The Miller capacitance
C
MILLER
)
+
− V
TH
• f
MILLER
OSC
DS
DS
, a
to
(1 + δ) is generally given for a MOSFET in the form of a
normalized R
curve, use δ = 0.005/°C • ΔT for low voltage MOSFETs.
The secondary-side power MOSFETs typically operate
at substantially lower V
losses. The dissipation is calculated using:
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
where T
junction to ambient thermal resistance.
Once you have T
δ and power dissipations until convergence.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves effi ciency
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer effi ciency.
The LTC4268-1 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with
maximum V
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchro-
nous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary as shown in the
application on the front page of this data sheet.
P
T
J
DIS(SEC)
= T
A
A
is the ambient temperature and θ
+ P
GS
= I
DS(ON)
DIS
RMS(SEC)
of 10V and larger.
J
• θ
vs temperature curve. If you don’t have a
iterate your calculations recomputing
JA
DS
2
• R
, so you can neglect transition
DS(ON)
(1 + δ)
LTC4268-1
JA
is the MOSFET
41
42681fb