LM25061PMM-2/NOPB National Semiconductor, LM25061PMM-2/NOPB Datasheet - Page 12

• Manufacturer Part Number: LM25061PMM-2/NOPB
• Description: IC CTLR POS HOTSWAP AUTO 10MSOP
• Manufacturer: National Semiconductor
• Type: Hot-Swap Controllerr

Specifications of LM25061PMM-2/NOPB

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.9 V ~ 17 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM25061PMM-2

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Under-Voltage Lock-Out (UVLO)
The series pass MOSFET (Q1) is enabled when the input
supply voltage (V
der-voltage lockout (UVLO) level. Typically the UVLO level at
V
1. Refering to the Block Diagram when V
LO level, the internal 20 µA current source at UVLO is en-
abled, and Q1 is held off by the 2 mA pull-down current at the
GATE pin. As V
above its threshold the 20 µA current source at UVLO is
switched off, increasing the voltage at UVLO, providing hys-
teresis for this threshold. With the UVLO pin above its thresh-
old, Q1 is switched on by the 20 µA current source at the
GATE pin if the insertion time delay has expired. See the Ap-
plications Section for a procedure to calculate the values of
the threshold setting resistors (R1-R2). The minimum possi-
ble UVLO level at V
pin to VIN. In this case Q1 is enabled after the insertion time.
Shutdown Control
The load current can be remotely switched off by taking the
UVLO pin below its threshold with an open collector or open
drain device, as shown in
pin the LM25061 switches on the load current with in-rush
current and power limiting.
SYS
is set with a resistor divider (R1-R2) as shown in
FIGURE 6. Shutdown Control
SYS
SYS
is increased, raising the voltage at UVLO
SYS
) is greater than the programmable un-
can be set by connecting the UVLO
Figure
6. Upon releasing the UVLO
SYS
FIGURE 5. Restart Sequence (LM25061-2)
is below the UV-
Figure
30090317
12
Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain
of an internal N-channel MOSFET capable of sustaining 17V
in the off-state, and transients up to 20V. An external pull-up
resistor is required at PGD to an appropriate voltage to indi-
cate the status to downstream circuitry. The off-state voltage
at the PGD pin can be higher or lower than the voltages at
VIN and OUT. The PGD pin switches high when the voltage
at the FB pin exceeds its threshold. Typically the output volt-
age threshold is set with a resistor divider (R3-R4) as shown
in Figure 1, although the monitored voltage need not be the
output voltage. Any other voltage can be monitored by con-
necting R3 to that voltage as long as the voltage at the FB pin
does not exceed its maximum rating. Referring to the Block
Diagram, when the voltage at the FB pin is below its threshold,
the internal 22 µA current source at FB is disabled. As the
output voltage increases, taking FB above its threshold, the
current source is enabled, sourcing current out of the pin,
raising the voltage at FB to provide threshold hysteresis.
The PGD output is low when the UVLO pin is below its thresh-
old. The PGD output is high when the voltage at VIN is less
than 1.6V.
Application Information
(Refer to Figure 1)
CURRENT LIMIT, R
The LM25061 monitors the current in the external MOSFET
(Q1) by measuring the voltage across the sense resistor
(R
value is calculated from:
where I
across R
the gate of Q1 to regulate the current at I
limiting circuit is active, the fault timer is active as described
in the Fault Timer & Restart section. For proper operation,
R
While the maximum load current in normal operation can be
used to determine the required power rating for resistor R
S
S
must be no larger than 200 mΩ.
), connected from VIN to SENSE. The required resistor
LIM
S
is the desired current limit threshold. If the voltage
reaches 50 mV, the current limit circuit modulates
S
30090316
LIM
. While the current
(1)
S
,