LM25061PMM-2/NOPB National Semiconductor, LM25061PMM-2/NOPB Datasheet - Page 17

• Manufacturer Part Number: LM25061PMM-2/NOPB
• Description: IC CTLR POS HOTSWAP AUTO 10MSOP
• Manufacturer: National Semiconductor
• Type: Hot-Swap Controllerr

Specifications of LM25061PMM-2/NOPB

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.9 V ~ 17 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM25061PMM-2

If a delay is required at PGD, suggested circuits are shown in
Figure 15. In Figure 15a, capacitor C
ing edge, but not to the falling edge. In Figure 15b, the rising
edge is delayed by R
edge is delayed a lesser amount by R
diode across R
two edges, or a short delay at the rising edge and a long delay
at the falling edge.
Design-in Procedure
The recommended design-in procedure is as follows:
•
•
•
Determine the current limit threshold (I
must be higher than the normal maximum load current,
allowing for tolerances in the current sense resistor value
and the LM25061 Current Limit threshold voltage. Use
equation 1 to determine the value for R
Determine the maximum allowable power dissipation for
the series pass FET (Q1), using the device’s SOA
information. Use equation 2 to determine the value for
R
Determine the value for the timing capacitor at the TIMER
pin (C
period (t
time. The turn-on time can be estimated using the
equations in the TURN-ON TIME section of this data
sheet, but should be verified experimentally. Review the
resulting insertion time, and restart timing if the
LM25061-2 is used.
PWR
.
T
) using equation 3 or equation 4. The fault timeout
FAULT
FIGURE 14. Power Good Output
PG2
) must be longer than the circuit’s turn-on-
(Figure 15c) allows for equal delays at the
PG1
+ R
PG2
FIGURE 15. Adding Delay to the Power Good Output Pin
and C
PG
PG2
adds delay to the ris-
PG
LIM
and C
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, while the falling
.
). This threshold
PG
. Adding a
17
•
•
•
PC Board Guidelines
The following guidelines should be followed when designing
the PC board for the LM25061:
•
•
•
•
•
•
•
Choose option A or B from the UVLO section of the
Application Information for setting the UVLO threshold and
hysteresis. Use the procedure for the appropriate option
to determine the resistor values at the UVLO pin.
Choose the appropriate voltage, and pull-up resistor, for
the Power Good output.
Determine the resistor values for the FB pin.
Place the LM25061 close to the board’s input connector
to minimize trace inductance from the connector to the
FET.
Place a small capacitor (1000 pF) directly adjacent to the
VIN and GND pins of the LM25061 to help minimize
transients which may occur on the input supply line.
Transients of several volts can easily occur when the load
current is shut off.
The sense resistor (R
and connected to it using the Kelvin techniques shown in
Figure
The high current path from the board’s input to the load
(via Q1), and the return path, should be parallel and close
to each other to minimize loop inductance.
The ground connection for the various components
around the LM25061 should be connected directly to each
other, and to the LM25061’s GND pin, and then connected
to the system ground at one point. Do not connect the
various component grounds to each other through the high
current ground line.
Provide adequate heat sinking for the series pass device
(Q1) to help reduce stresses during turn-on and turn-off.
The board’s edge connector can be designed to shut off
the LM25061 as the board is removed, before the supply
voltage is disconnected from the LM25061. In
the voltage at the UVLO pin goes to ground before V
is removed from the LM25061 due to the shorter edge
connector pin. When the board is inserted into the edge
connector, the system voltage is applied to the LM25061’s
VIN pin before the UVLO voltage is taken high.
7.
S
) should be close to the LM25061,
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Figure 16
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