LM25061PMM-2/NOPB National Semiconductor, LM25061PMM-2/NOPB Datasheet - Page 15

• Manufacturer Part Number: LM25061PMM-2/NOPB
• Description: IC CTLR POS HOTSWAP AUTO 10MSOP
• Manufacturer: National Semiconductor
• Type: Hot-Swap Controllerr

Specifications of LM25061PMM-2/NOPB

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.9 V ~ 17 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM25061PMM-2

MOSFET SELECTION
It is recommended that the external MOSFET (Q1) selection
be based on the following criteria:
-
system voltage (V
occur at V
inserted or removed.
-
on the current limit threshold (50 mV/R
load current, since the circuit can operate near the current
limit threshold continuously.
-
the current threshold for the circuit breaker function (95 mV/
R
-
the thermal properties, should be used to determine the max-
imum power dissipation threshold set by the R
The programmed maximum power dissipation should have a
reasonable margin from the maximum power defined by the
FET's SOA chart if the LM25061-2 is used since the FET will
be repeatedly stressed during fault restart cycles. The FET
manufacturer should be consulted for guidelines.
-
tion at maximum load current (I
its junction temperature above the manufacturer’s recom-
mendation.
If the circuit’s input voltage is at the low end of the LM25061’s
operating range (<3.5V), or at the high end of the operating
range (>14V), the gate-to-source voltage applied to the MOS-
FET by the LM25061 is less than 5V, and can approach 1V
in a worst case situation. See the graph “GATE Pin Voltage”.
The selected device must have a suitable Gate-to-Source
Threshold Voltage.
The gate-to-source voltage provided by the LM25061 can be
as high as 19.5V at turn-on when the output voltage is zero.
At turn-off the reverse gate-to-source voltage will be equal to
the output voltage at the instant the GATE pin is pulled low.
If the device chosen for Q1 is not rated for these voltages, an
external zener diode must be added from its gate to source,
with the zener voltage less than the device maximum V
rating. The zener diode’s working voltage protects the MOS-
FET during turn-on, and its forward voltage protects the MOS-
FET during shutoff. The zener diode’s forward current rating
must be at least 260 mA to conduct the GATE pull-down cur-
rent when a circuit breaker condition is detected.
TIMER CAPACITOR, C
The TIMER pin capacitor (C
time delay, fault timeout period, and restart timing of the
LM25061-2.
A) Insertion Delay - Upon applying the system voltage
(V
during the insertion time (t1 in
transients at V
to a circuit card plug-in is unique, the worst case settling time
must be determined for each application. The insertion time
starts when VIN reaches the POR threshold, at which time the
internal 5.5 µA current source charges C
The required capacitor value is calculated from:
S
SYS
).
The Pulsed Drain Current spec (I
The maximum continuous current rating should be based
The SOA (Safe Operating Area) chart of the device, and
The BV
R
DS(on)
) to the circuit, the external MOSFET (Q1) is held off
SYS
should be sufficiently low that the power dissipa-
DSS
SYS
when the circuit card, or adjacent cards, are
rating should be greater than the maximum
SYS
to settle. Since each backplane’s response
), plus ringing and transients which can
T
T
) sets the timing for the insertion
L(max)
Figure
2
DM
x R
3) to allow ringing and
) must be greater than
S
DS(on)
), not the maximum
T
from 0V to 1.72V.
) does not raise
PWR
resistor.
GS
15
For example, if the desired insertion delay is 250 ms, C
culates to 0.8 µF. At the end of the insertion delay, C
quickly discharged by a 2 mA current sink.
B) Fault Timeout Period - During in-rush current limiting or
upon detection of a fault condition where the current limit and/
or power limit circuits regulate the current through Q1, the
fault timer current source (80 µA) switches on to charge C
The Fault Timeout Period is the time required for the voltage
at the TIMER pin to transition from ground to 1.72V, at which
time Q1 is switched off. If the LM25061-1 is in use, the re-
quired capacitor value is calculated from:
For example, if the desired Fault Timeout Period is 17 ms,
C
pires, the LM25061-1 latches the GATE pin low until a power-
up sequence is initiated by external circuitry. If the LM25061-2
is in use, the Fault Timeout Period during restart cycles is
approximately 18% shorter than the initial fault timeout period
which initiated the restart cycles since the voltage at the
TIMER pin transitions from 0.3V to 1.72V. Since the Fault
Timeout Period must always be longer than the turn-on-time,
the required capacitor value for the LM25061-2 is calculated
using this shorter time period:
For example, if the desired Fault Timeout Period is 17 ms,
C
the LM25061-2 expires, a restart sequence starts as de-
scribed below (Restart Timiing). Since the LM25061 normally
operates in power limit and/or current limit during a power-up
sequence, the Fault Timeout Period MUST be longer than the
time required for the output voltage to reach its final value.
See the Turn-on Time section
C) Restart Timing For the LM25061-2, after the Fault Time-
out Period described above, C
current sink to 1.0V. The TIMER pin then cycles through sev-
en additional charge/discharge cycles between 1V and 1.72V
as shown in
pin voltage reaches 0.3V during the final high-to-low ramp.
The restart time, after the Fault Timeout Period, is equal to:
For example, if C
end of the restart time, Q1 is switched on. If the fault is still
present, the fault timeout and restart sequence repeats. The
on-time duty cycle of Q1 is approximately 0.67% in this mode.
UVLO
Programming the UVLO thresholds sets the minimum system
voltage to enable the series pass device (Q1). If V
the UVLO thresholds, Q1 is switched off, denying power to
the load. Programmable hysteresis is provided.
Option A: The UVLO thresholds are set with two resistors
(R1, R2) as shown in Figure 11.
T
T
calculates to 0.8 µF. When the Fault Timeout Period ex-
calculates to 0.96 µF. When the Fault Timeout Period of
Figure
T
= 0.8 µF, t
5. The restart time ends when the TIMER
= C
T
x 2.65 x 10
RESTART
T
is discharged by the 2.5 µA
= 2.12 seconds. At the
6
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SYS
is below
T
cal-
T
(3)
(4)
is
T
.