ISL6142IBZA Intersil, ISL6142IBZA Datasheet - Page 15

• Manufacturer Part Number: ISL6142IBZA
• Description: IC CTRLR HOT PLUG NEG 14-SOIC
• Manufacturer: Intersil
• Type: Hot-Swap Controllerr

Specifications of ISL6142IBZA

• Applications: General Purpose, VoIP
• Internal Switch(s): No
• Voltage - Supply: 36 V ~ 72 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The values of R4 = 549K, R5 = 6.49K, and R6 = 10K shown
in figure 29 set the Under-Voltage threshold at 43V, and the
Over-Voltage, turn off threshold to 71V. The Under-Voltage
(UV) comparator has a hysteresis of 135mv’s (4.6V of
hysteresis on the supply) which correlates to a 38.4V turn off
voltage. The Over-Voltage comparator has a 25mv
hysteresis (1.4V of hysteresis on the supply) which
translates to a turn on voltage (supply decreasing) of
approximately 69.6V.
Q1 - is the FET that connects the input supply voltage to the
output load, when properly enabled. It needs to be selected
based on several criteria:
• Maximum voltage expected on the input supply (including
• Maximum current and power dissipation expected during
• Power dissipation and/or safe-operating-area
• Other considerations include the GATE voltage threshold
R1 - is the Over-Current sense resistor also referred to as
R
voltage drop across R1 exceeds the SENSE comparator trip
point (50mV nominal), the GATE pin will be pulled lower (to
~4V) and current will be regulated to 50mV/Rsense for the
programmed time-out period which is set by C3. The Over-
Current threshold is defined in Equation 3 below. If the time-
out period is exceeded the Over-Current latch will be set and
the FET will be turned off to protect the load from excessive
current. A typical value for R1 is 0.02Ω, which sets an Over-
Current trip point of; I
select the appropriate value for R1, the user must first
determine at what level of current it should trip, take into
account worst case variations for the trip point (50mV
±10mV = ±20%), and the tolerances of the resistor (typically
1% or 5%). Note that the Over-Current threshold should be
set above the inrush current level plus the expected load
current to avoid activating the current limit and time-out
circuitry during start-up. If the power good output
(PWRGD/PWRGD) is used to enable an external module,
the desired inrush current only needs to be considered. One
rule of thumb is to set the Over-Current threshold 2-3 times
higher than the normal operating current.
The physical layout of the R1 sense resistor is critical to
avoid the possibility of false over current events. Since it is in
the main input-to-output path, the traces should be wide
enough to support both the normal current, and currents up
to the over-current trip point. The trace routing between the
SENSE
transients) as well as transients on the output side.
normal operation, usually at a level just below the current
limit threshold.
considerations during current limiting and single retry
events.
which affects the r
voltage drop across the FET during normal operation),
and the maximum gate voltage allowed (the IC’s GATE
output is clamped to ~14V).
I
OC
=
. If the input current is high enough, such that the
------------------- -
R
50mv
sense
DS(ON)
OC
= V/R = 0.05/0.02 = 2.5 Amps. To
(which in turn, affects the
15
(EQ. 3)
ISL6142, ISL6152
R1 resistor, and the V
and as short as possible with zero current in the sense lines.
Note that in figure 30 the traces from each side of the R1
resistor also connect to the R8 (IS+), and R7 (IS-) current
sensing resistors.
CL - is the sum of all load capacitances, including the load’s
input capacitance itself. Its value is usually determined by
the needs of the load circuitry, and not the hot plug (although
there can be interaction). For example, if the load is a
regulator, then the capacitance may be chosen based on the
input requirements of that circuit (holding regulation under
current spikes or loading, filtering noise, etc.) The value
chosen will affect the peak inrush current. Note that in the
case of a regulator, there may be capacitors on the output of
that circuit as well; these need to be added into the
capacitance calculation during inrush (unless the regulator is
delayed from operation by the PWRGD/PWRGD signal).
RL - is the equivalent resistive value of the load and
determines the normal operating current delivered through
the FET. It also affects some dynamic conditions (such as
the discharge time of the load capacitors during a power-
down). A typical value might be 48Ω (I=V/R = 48/48 = 1A).
R2, C1, R3, C2 - are related to the GATE driver, as it
controls the inrush current.
R2 prevents high frequency oscillations; 10Ω is a typical
value. R2 = 10Ω.
R3 and C2 act as a feedback network to control the inrush
current as shown in equation 4, where CL is the load
capacitance (including module input capacitance), and I
the GATE pin charging current, nominally 50µA.
Begin by choosing a value of acceptable inrush current for
the system, and then solve for C2.
CORRECT
To V
and R7
To SENSE
FIGURE 30. SENSE RESISTOR LAYOUT GUIDELINES
and R8
EE
I
SENSE RESISTOR
EE
inrush
CURRENT
and SENSE pins should be direct
=
INCORRECT
I
PU
×
C
------ -
C
L
2
(EQ. 4)
PU
is