ISL6594DCBZ Intersil, ISL6594DCBZ Datasheet - Page 6

• Manufacturer Part Number: ISL6594DCBZ
• Description: IC MOSFET DRVR SYNC BUCK 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6594DCBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 10.0ns
• Current - Peak: 1.25A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Description
Operation
Designed for versatility and speed, the ISL6594D MOSFET
driver controls both high-side and low-side N-Channel FETs
of a half-bridge power train from one externally provided
PWM signal.
Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated during initial
start-up; the upper gate (UGATE) is held low and the lower
gate (LGATE), controlled by the Pre-POR overvoltage
protection circuits, is connected to the PHASE. Once the
VCC voltage surpasses the VCC Rising Threshold (see
“Electrical Specifications” on page 4), the PWM signal takes
control of gate transitions. A rising edge on PWM initiates
the turn-off of the lower MOSFET (see Timing Diagram on
page 6). After a short propagation delay [t
gate begins to fall. Typical fall times [t
“Electrical Specifications” on page 4. Adaptive shoot-through
circuitry monitors the LGATE voltage and determines the
upper gate delay time [t
and upper MOSFETs from conducting simultaneously. Once
this delay period is complete, the upper gate drive begins to
rise [t
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t
circuitry determines the lower gate delay time, t
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next section for
details). The lower gate then rises [t
MOSFET.
PWM
UGATE
RU
LGATE
t
] and the upper MOSFET turns on.
PDLL
FU
PDLU
]. Again, the adaptive shoot-through
PDHU
] is encountered before the upper
t
FL
]. This prevents both the lower
6
t
PDHU
RL
t
RU
FL
], turning on the lower
t
PDHL
] are provided in the
PDLL
], the lower
PDHL
t
RL
FIGURE 1. TIMING DIAGRAM
t
PDLU
. The
t
FU
ISL6594D
1.18V < PWM < 2.36V
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The ISL6594D driver incorporates a unique adaptive
deadtime control technique to minimize deadtime, resulting
in high efficiency from the reduced freewheeling time of the
lower MOSFETs’ body-diode conduction, and to prevent the
upper and lower MOSFETs from conducting simultaneously.
This is accomplished by ensuring either rising gate turns on
its MOSFET with minimum and sufficient delay after the
other has turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.2V/+0.8V trip point within
15ns for a forward/reverse current, at which time the UGATE
turns on after 10ns propagation delay. An auto-zero
comparator is used to correct the r
voltage preventing from false detection of the -0.2V phase
level during r
current and/or 15ns phase detect expired, the UGATE turns
on after 10ns propagation delay. During the phase detection,
the disturbance of LGATE’s falling transition on the PHASE
node is blanked out to prevent falsely tripping. Once the
PHASE is high, the advanced adaptive shoot-through
circuitry monitors the PHASE and UGATE voltages during a
PWM falling edge and the subsequent UGATE turn-off. If
either the UGATE falls to less than 1.75V above the PHASE
or the PHASE falls to less than +0.8V, the LGATE is
released to turn on after 10ns propagation delay.
Three-State PWM Input
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set hold-off time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
t
TSSHD
DS(ON)
t
PDTS
conduction period. In the case of zero
0.76V < PWM < 1.96V
DS(ON)
t
TSSHD
drop in the phase
December 3, 2007
t
PDTS
FN9282.1