HIP2100EIB Intersil, HIP2100EIB Datasheet
HIP2100EIB
Specifications of HIP2100EIB
Available stocks
Related parts for HIP2100EIB
HIP2100EIB Summary of contents
Page 1
... MARKING (°C) HIP2100IB 2100 IB -40 to +125 8 Ld SOIC HIP2100IBZ 2100 IBZ -40 to +125 8 Ld SOIC (Note 2) HIP2100EIBZ 2100 EIBZ -40 to +125 8 Ld EPSOIC (Note 2) HIP2100IRZ HIP 2100IRZ -40 to +125 16 Ld 5x5 QFN (Note 2) HIP2100IR4Z 21 00IR4Z -40 to +125 12 Ld 4x4 DFN ...
Page 2
Pinouts HIP2100 (8 LD SOIC, EPSOIC) TOP VIEW EPAD NOTE: EPAD = Exposed PAD. Application Block Diagram PWM CONTROLLER 2 HIP2100 HIP2100IR4 ...
Page 3
Functional Block Diagram *EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PCB power ground plane. +12V PWM +12V PWM FIGURE ...
Page 4
... Max Power Dissipation at +25°C in Free Air (EPSOIC, Note 3.1W Max Power Dissipation at +25°C in Free Air (QFN, Note 3.3W Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature Range .-55°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp - +100V DD DD ...
Page 5
Electrical Specifications PARAMETERS BOOT STRAP DIODE Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance LO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pullup Current Peak Pulldown Current HO GATE DRIVER Low Level ...
Page 6
Pin Descriptions SYMBOL V Positive Supply to lower gate drivers. De-couple this pin High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. HO High-Side ...
Page 7
Typical Performance Curves 500 12V 400 14V HB DD 300 200 100 - TEMPERATURE (°C) FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE ...
Page 8
Typical Performance Curves 2.5 2.0 1.5 1 FIGURE 13. PEAK PULLDOWN CURRENT vs OUTPUT VOLTAGE ...
Page 9
... The pin #1 identifier may be either a mold or mark feature. improved electrical and thermal performance. Design efforts, see Intersil Technical Brief TB389. the L dimension. MAX NOTES 0.90 - 0.05 - ...
Page 10
... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation ...
Page 11
Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
Page 12
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...