LM2642MTC/NOPB

Manufacturer Part NumberLM2642MTC/NOPB
DescriptionIC CTRLR SW SYNC STPDN 28TSSOP
ManufacturerNational Semiconductor
LM2642MTC/NOPB datasheet
 


Specifications of LM2642MTC/NOPB

ApplicationsEmbedded systems, Console/Set-Top boxesCurrent - Supply1mA
Voltage - Supply4.5 V ~ 30 VOperating Temperature-40°C ~ 125°C
Mounting TypeSurface MountPackage / Case28-TSSOP
Dc To Dc Converter TypeSynchronous Step Down ControllerNumber Of Outputs2
Pin Count28Input Voltage4.5 to 30V
Output Voltage1.3 to 30VOutput Current20A
Package TypeTSSOPMountingSurface Mount
Operating Temperature ClassificationAutomotiveOperating Temperature (min)-40C
Operating Temperature (max)125CPrimary Input Voltage30V
No. Of Outputs1No. Of Pins28
Operating Temperature Range-40°C To +125°CMslMSL 3 - 168 Hours
Control ModeCurrentRohs CompliantYes
For Use WithLM2642REVD EVAL - BOARD EVALUATION LM2642Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names*LM2642MTC
*LM2642MTC/NOPB
LM2642MTC
  
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Operation Descriptions
typical) both channels will latch off. Also, UV_DELAY will be
disabled and the UV_DELAY pin will return to 0V. During
UVP, both the high side and low side FET drivers will be
turned off. If no capacitor is connected to the UV_DELAY pin,
the UVP latch will be activated immediately. To reset the
UVP latch, either the input voltage must be cycled, or both
ON/SS pins must be pulled low. The UVP function can be
disabled by connecting the UV_DELAY pin to ground.
POWER GOOD
A power good pin (PGOOD1) is available to monitor the
output status of Channel 1. As shown in Figure 5, the pin
connects to the output of an open drain MOSFET, which will
remain open while Channel 1 is within operating range.
PGOOD1 will go low (low impedance to ground) under the
following four conditions:
1. Channel 1 is turned off
2. Channel 1 output falls below 90.3% of nominal (UVPG1)
3. OVP on either channel
4. UVP on either channel
When on, the PGOOD1 pin is capable of sinking 0.95mA
(typical). If an OVP or UVP condition occurs, both channels
will latch off, and the PGOOD1 pin will be latched low. During
a UVPG1 condition, however, PGOOD1 will not latch off. The
pin will stay low until Channel 1 output voltage returns to
94% (typical) of nominal. See Vpwrgd in the Electrical Char-
acteristics table.
OUTPUT CAPACITOR DISCHARGE
Each channel has an embedded 480Ω MOSFET with the
drain connected to the SWx pin. This MOSFET will dis-
charge the output capacitor of its channel if its channel is off,
or the IC enters a fault state caused by one of the following
conditions:
1. UVP
2. UVLO
3. Thermal shut-down (TSD)
If an output over voltage event occurs, the HDRVx will be
turned off and LDRVx will be turned on immediately to
discharge the output capacitor of both channels through the
inductor.
BOOTSTRAP DIODE SELECTION
The bootstrap diode and capacitor form a supply that floats
above the switch node voltage. VLIN5 powers this supply,
creating approximately 5V (minus the diode drop) which is
used to power the high side FET drivers and driver logic.
When selecting a bootstrap diode, Schottky diodes are pre-
ferred due to their low forward voltage drop, but care must be
taken for circuits that operate at high ambient temperature.
The reverse leakage of some Schottky diodes can increase
by more than 1000x at high temperature, and this leakage
path can deplete the charge on the bootstrap capacitor,
starving the driver and logic. Standard PN junction diodes
and fast rectifier diodes can also be used, and these types
maintain tighter control over reverse leakage current across
temperature.
SWITCHING NOISE REDUCTION
Power MOSFETs are very fast switching devices. In syn-
chronous rectifier converters, the rapid increase of drain
current in the top FET coupled with parasitic inductance will
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generate unwanted Ldi/dt noise spikes at the source node of
(Continued)
the FET (SWx node) and also at the VIN node. The magni-
tude of this noise will increase as the output current in-
creases. This parasitic spike noise may turn into electromag-
netic interference (EMI), and can also cause problems in
device performance. Therefore, it must be suppressed using
one of the following methods.
It is strongly recommended to add R-C filters to the current
sense amplifier inputs as shown in Figure 7. This will reduce
the susceptibility to switching noise, especially during heavy
load transients and short on time conditions. The filter com-
ponents should be connected as close as possible to the IC.
Note that these filters should be used when a current sense
resistor is used.
As shown in Figure 6, adding a resistor in series with the
SWx pin will slow down the gate drive (HDRVx), thus slowing
the rise and fall time of the top FET, yielding a longer drain
current transition time.
Usually a 3.3Ω to 4.7Ω resistor is sufficient to suppress the
noise. Top FET switching losses will increase with higher
resistance values.
Small resistors (1-5 ohms) can also be placed in series with
the HDRVx pin or the CBOOTx pin to effectively reduce
switch node ringing. A CBOOT resistor will slow the rise time
of the FET, whereas a resistor at HDRV will reduce both rise
and fall times.
FIGURE 6. SW Series Resistor
CURRENT SENSING AND LIMITING
As shown in Figure 7, the KSx and RSNSx pins are the
inputs of the current sense amplifier. Current sensing is
accomplished either by sensing the Vds of the top FET or by
sensing the voltage across a current sense resistor con-
nected from VIN to the drain of the top FET. The advantage
of sensing current across the top FET are reduced parts
count, cost and power loss, whereas using a current sense
resistor improves the current sense accuracy. Keeping the
differential current-sense voltage below 200mV ensures lin-
ear operation of the current sense amplifier. Therefore, the
Rdson of the top FET or the current sense resistor must be
small enough so that the current sense voltage does not
exceed 200mV when the top FET is on. There is a leading
edge blanking circuit that forces the top FET on for at least
166ns. Beyond this minimum on time, the output of the PWM
comparator is used to turn off the top FET. Additionally, a
minimum voltage of at least 50mV across Rsns is recom-
mended to ensure a high SNR at the current sense amplifier.
Assuming a maximum of 200mV across Rsns, the current
sense resistor can be calculated as follows:
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