ISL6218CVZA-T Intersil, ISL6218CVZA-T Datasheet - Page 11

• Manufacturer Part Number: ISL6218CVZA-T
• Description: IC CTRLR INTEL PENT M 38-TSSOP
• Manufacturer: Intersil

Specifications of ISL6218CVZA-T

• Applications: Processor
• Current - Supply: 1.4mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Deep Sleep Enable (DSEN) and Deeper Sleep
Enable (DRSEN)
Table 2 shows logic states controlling modes of operation
Figure 6 and Figure 5 show the timing for transitions entering
and exiting Deep Sleep Mode and Deeper Sleep Mode,
controlled by the system signals STPCPU and DPRSLPVR.
Pins DSEN (Deep Sleep Enable) and DRSEN (Deeper
Sleep Enable) of the ISL6218 are connected to these 2
signals, respectively.
For the case when DSEN is logic high, and DRSEN is logic
low, the controller will operate in Active Mode and regulate
the output voltage to the VID commanded DAC voltage
minus the voltage “Droop” as determined by the load current.
Voltage “Droop” is the reduction of output voltage
proportional to output current.
FIGURE 5. PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING
FIGURE 6. CORE VOLTAGE SLEWING TO 98.8% OF PROGRAMMED VID VOLTAGE FOR A LOGIC LEVEL LOW ON DSEN
VID[0..5]
PGOOD
V
VID[0..5]
CC_CORE
STP_CPU
(DSEN)
DPRSLPVR
(DRSEN)
V
VID[0..5]
V
CC_CORE
STP_CPU
(DSEN)
CC_CORE
VID COMMAND VOLTAGE
V
CURRENT VOLTAGE LEVEL
DEEP
11
HIGH
CURRENT VID CODE
FIGURE 7. VCORE RESPONSE FOR DEEPER SLEEP COMMAND
V
DEEPER
<600ns
V
DEEP SLEEP
DEEPER SLEEP
SHORT DPRSLP CAUSES V
VID CODE REMAINS THE SAME
VID CODE REMAINS THE SAME
ISL6218
NEW VID CODE
When a logic low is seen on the DSEN and DRSEN is logic
low the controller will then regulate the output voltage to the
voltage seen on the DSV pin minus “Droop”.
When DSEN is logic low and DRSEN is logic high the
controller will operate in Deeper Sleep mode. The ISL6218
will then regulate to the voltage seen on the DRSV pin minus
“Droop”.
Deep and Deeper Sleep voltage levels are programmable
and explained in “STV, DSV and DRSV” on page 12.
DISCONTINUOUS OPERATION - PSI
The ISL6218 Single-Phase PWM controller is a
Synchronous Buck Regulator. However, in Deep and Deeper
Sleep modes where the load current is low, the controller
operates as a standard buck regulator. This mode of
operation acts to eliminate negative inductor current by
truncating the low side MOSFET gate drive pulse, and
NEW VOLTAGE LEVEL
CC_CORE
TO RAMP-UP
<3µs
August 6, 2007
FN9101.6