ISL6218CVZA-T Intersil, ISL6218CVZA-T Datasheet - Page 14

• Manufacturer Part Number: ISL6218CVZA-T
• Description: IC CTRLR INTEL PENT M 38-TSSOP
• Manufacturer: Intersil

Specifications of ISL6218CVZA-T

• Applications: Processor
• Current - Supply: 1.4mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ISL6218 controller regulates the CORE output voltage
to the VID command and once the timer has expired, the
PGOOD output is allowed to go high.
Note, the PGOOD functions of the V
Vcc_mch regulators are wire OR’d together to create the
system signal “IMVP4_PWRGD”. If any of the supplies fall
outside the regulation window, their respective PGOOD pins
are pulled low, which forces IMVP4_PWRGD low. PGOOD
of the ISL6218 is internally disabled during all VID and Mode
transitions.
OVERVOLTAGE
The VSEN voltage is compared with an internal overvoltage
protection (OVP) reference set to 112% of the VID voltage. If
the VSEN voltage exceeds the OVP reference, a comparator
simultaneously sets the OV latch and triggers the PWM
output low. The drivers turn on the lower MOSFETs,
shunting the converter output to ground. Once the output
voltage falls below 102% of the set point, the high side and
low side PWM outputs are held in “Three-State”.
This prevents dumping of the output capacitors back through
the output inductors and lower MOSFETs, which would
cause a negative voltage on the CORE output.
This architecture eliminates the need of a high current,
Schottky diode on the output. If the overvoltage conditions
persist, the PWM outputs are cycled between output low and
output “off”, similar to a hysteretic regulator. The OV latch is
reset by cycling the VDD supply voltage to initiate a POR.
Depending on the mode of operation, the overvoltage
setpoint is 112% of the VID, Deep or Deeper Sleep setpoint.
UNDERVOLTAGE
The VSEN pin is also compared to an Undervoltage (UV)
reference, which is set to 84% of the VID, Deep or Deeper
Sleep setpoint, depending on the mode of operation. If the
VSEN voltage is below the UV reference for more than 32
consecutive phase clock cycles, the power good monitor
triggers the PGOOD pin to go low and latches the chip off
until power is reset to the chip or the EN pin is toggled.
OVERCURRENT
The R
lower MOSFET and provides current feedback I
proportional to the output current (refer to Figure 10). After
current sensing function, I
Diagram” on page 7 and Figure 10). I
an internally generated overcurrent trip threshold that is
propotional to the current sourced from the OCSET pin,
I
and described in “Overcurrent Setting - OCSET” on page 12.
If I
enabled. If I
cycle counts, the PGOOD pin transitions low and latches the
chip off. If normal operation resumes within the 32 phase
OCSET
SEN
ISEN
. The overcurrent trip current source is programmable
exceeds the I
resistor scales the voltage sampled across the
SEN
’ does not fall below I
OCSET
SEN
level, an up/down counter is
14
is obtained (refer to the “Block
CC_CORE
OCSET
SEN
is compared with
within 32 phase
, Vccp and
SEN
, which is
ISL6218
cycle count window, the controller will continue to operate
normally.
NOTE: Due to “DROOP”, there is inherent Current limit since
load current cannot exceed the amount that would command
an output voltage lower than 84% of the VID voltage. This
would result in an undervoltage shutdown and would also
cause the PGOOD pin to transition low and latch the chip off.
CONTROL LOOPS
Figure 10 shows a simplified diagram of the voltage
regulation and current control loops for a Single-Phase
converter. Both voltage and current feedback are used to
precisely regulate voltage and tightly control output current
I
Comparators, Internal Gate Drivers and MOSFETs. The
Error Amplifier drives the modulator to force the FB pin to the
IMVP-IV
VOLTAGE LOOP
The output CORE voltage feedback is applied to the Error
Amplifier through the compensation network. The signal
seen on the FB pin will drive the Error Amplifier output either
high or low, depending upon the CORE voltage. A CORE
voltage level that is lower than the IMVP-IV
output from the 6-bit DAC, causes the amplifier output to
move towards a higher output voltage level. The amplifier
output voltage is applied to the positive input of the
comparator. Increasing Error Amplifier voltage results in
increased Comparator output duty cycle. This increased duty
cycle signal is passed through the PWM circuit to the internal
gate drive circuitry. The output of the internal gate drive is
directly connected to the gate of the MOSFETs. Increased
duty cycle, or ON-time, for the high side MOSFET
transistors, results in increased output voltage (VCORE) to
compensate for the low output voltage sensed.
DROOP COMPENSATION
Microprocessors and other peripherals tend to change their
load current demands from near no-load to full load, often
during operation. These same devices require minimal
output voltage deviation during a load step.
A high di/dt load step will cause an output voltage spike. The
amplitude of the spike is dictated by the output capacitor
ESR multiplied by the load step magnitude plus the output
capacitor ESL times the load step di/dt. A positive load step
produces a negative output voltage spike and vice versa. A
large number of low-series-impedance capacitors are often
used to prevent the output voltage deviation from exceeding
the tolerance of some devices. One widely accepted solution
to this problem is output voltage “Droop”, or active voltage
positioning.
As shown in the block diagram, the sensed current (I
used to control the “Droop” current source, I
“Droop” current source is a controlled current source and is
proportional to output current. This current source is
L1
. The voltage loop is comprised of the Error Amplifier,
™
reference minus “Droop”.
™
DROOP
reference, as
August 6, 2007
. The
SEN
FN9101.6
) is