ADT7476ARQZ ON Semiconductor, ADT7476ARQZ Datasheet - Page 46

• Manufacturer Part Number: ADT7476ARQZ
• Description: IC REMOTE THERMAL CTRLR 24QSOP
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of ADT7476ARQZ

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Full Temp Accuracy: +/- 0.5 C
• Digital Output - Bus Interface: Serial (3-Wire, 4-Wire)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Fan Sync
to synchronize them so that one PWM channel from each
device can be effectively OR’ed together to create a PWM
output that reflects the maximum speed of the two OR’ed
PWMs. This OR’ed PWM can in turn be used to drive a
chassis fan.
Standby Mode
to the STBY supply. In computers that support S3 and S5
states, the core voltage of the processor is lowered in these
states. When monitoring THERM, the THERM timer
should be disabled during these states.
the following occurs:
limit, everything is re−enabled and the system resumes
normal operation.
XNOR Tree Test Mode
mode is useful for in−circuit test equipment at board−level
testing. By applying stimulus to the pins included in the
XNOR tree, it is possible to detect opens, or shorts, on the
system board.
the XNOR Tree Test Enable Register (0x6F).
When two ADT7476s are used in a system, it is possible
The ADT7476 has been specifically designed to respond
When the V
Once the core voltage, V
The ADT7476 includes an XNOR tree test mode. This
The XNOR tree test is invoked by setting Bit 0 (XEN) of
1. Status Bit 1 (V
2. SMBALERT is generated, if enabled.
3. THERM monitoring is disabled. The THERM
is set.
timer should hold its value prior to the S3 or S5
state.
CCP
voltage drops below the V
CCP
) in Interrupt Status Register 1
CCP
, goes above the V
CCP
low limit,
CCP
http://onsemi.com
low
46
XNOR tree test mode.
Power−On Default
default and the PWM outputs go to 100%. All necessary
registers then need to be configured via the SMBus for the
appropriate functions to operate.
Figure 66 shows the signals that are exercised in the
When the ADT7476 is powered up, monitoring is off by
Figure 66. XNOR Tree Test
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3
VID0
VID1
VID2
VID3
VID4
PWM1/XTO