LT1952EGN-1#PBF Linear Technology, LT1952EGN-1#PBF Datasheet - Page 15

• Manufacturer Part Number: LT1952EGN-1#PBF
• Description: IC CTLR PWM SGL SWITCH 16-SSOP
• Manufacturer: Linear Technology

Specifications of LT1952EGN-1#PBF

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 560kHz
• Duty Cycle: 90%
• Voltage - Supply: 6.82 V ~ 25 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-SSOP
• Frequency-max: 560kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
Programming Synchronous Rectifi er Timing:
SOUT to OUT delay (‘t
The LT1952/LT1952-1 have an additional output SOUT
which provides a ±50mA peak drive clamped to 12V. In
applications requiring synchronous rectifi cation for high
effi ciency, the LT1952/LT1952-1 SOUT provides a sync
signal for secondary side control of the synchronous
rectifi er MOSFETs (Figure 11). Timing delays through the
converter can cause non-optimum control timing for the
synchronous rectifi er MOSFETs. The LT1952/LT1952-1
provide a programmable delay (t
SOUT rising edge and OUT rising edge to optimize timing
control for the synchronous rectifi er MOSFETs to achieve
maximum effi ciency gains. A resistor R
from the DELAY pin to ground sets the value of t
Typical values for t
10k to 160ns with R
Performance Characteristics)
Programming Maximum Duty Cycle Clamp
For forward converter applications using the simplest
topology of a single MOSFET on the primary, a maximum
switch duty cycle clamp which adapts to transformer
input voltage is necessary for reliable control of the
MOSFET. This volt-second clamp provides a safeguard for
transformer reset that prevents transformer saturation. The
LT1952/LT1952-1 SD_V
capacitor-less, programmable volt-second clamp solution
using simple resistor ratios (Figure 9).
An increase of voltage at the SD_V
maximum duty cycle clamp to decrease. Deriving SD_V
from a resistor divider connected to system input voltage
creates the volt-second clamp. The maximum duty cycle
clamp can be adjusted by programming voltage on the
Figure 8. Programming SOUT to OUT Delay: t
SOUT
OUT
t
DELAY
DELAY
DELAY
DELAY
SEC
range from 10ns with R
and SS_MAXDC pins provide a
= 160k. (see graph in Typical
’)
LT1952-1
LT1952/
DELAY
DELAY
1952 F08
SEC
, Figure 8) between
DELAY
pin causes the
R
DELAY
DELAY
connected
DELAY
DELAY
SEC
=
.
SS_MAXDC pin using a resistor divider from V
increase of voltage at the SS_MAXDC pin causes the
maximum duty cycle clamp to increase.
To program the volt-second clamp, the following steps
should be taken:
(1)The maximum operational duty cycle of the converter
(2)An initial value for the maximum duty cycle clamp
Note: Since maximum operational duty cycle occurs at
minimum system input voltage (UVLO), the voltage at the
SD_V
where,
(3) The maximum duty cycle clamp calculated in (2) should
be programmed to be 10% greater than the maximum
operational duty cycle calculated in (1). Simple adjust-
ment of maximum duty cycle can be achieved by adjusting
SS_MAXDC.
should be calculated for the given application.
should be calculated using the equation below with a
fi rst pass guess for SS_MAXDC.
Max Duty Cycle Clamp (OUT pin)
= k • 0.522(SS_MAXDC(DC)/SD_V
(t
SS_MAXDC(DC) = V
SD_V
t
k = 1.11 – 5.5e
DELAY
DELAY
SEC
Figure 9. Programming Maximum Duty Cycle Clamp
CLAMP INPUT
DUTY CYCLE
SEC
pin = 1.32V.
ADAPTIVE
• f
= programmed delay between SOUT and OUT
= 1.32V at minimum system input voltage
OSC
*MINIMUM ALLOWABLE R
)
GUARANTEE SOFT-START PULL-OFF
–7
INPUT VOLTAGE
SYSTEM
• (f
REF
LT1952/LT1952-1
OSC
R1
R2
(R
)
R
B
B
/(R
R
T
*
T
MAX DUTY CYCLE
CLAMP ADJUST INPUT
T
IS 10k TO
SD_V
SS_MAXDC
V
+ R
REF
LT1952-1
SEC
LT1952/
SEC
B
)
) –
1952 F09
REF
15
19521fd
. An