HIP6021CBZ Intersil, HIP6021CBZ Datasheet - Page 7

• Manufacturer Part Number: HIP6021CBZ
• Description: IC PWM TRPL PWR CONTROL 28-SOIC
• Manufacturer: Intersil

Specifications of HIP6021CBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 4
• Frequency - Max: 215kHz
• Duty Cycle: 100%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: Yes
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 215kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

error amplifier. Similarly, the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-mode
control feedback loop of the synchronous PWM converter.
VSEN1 (Pin 22)
This pin is connected to the PWM converter’s output voltage.
The PGOOD and OVP comparator circuits use this signal to
report output voltage status and for over- voltage protection.
DRIVE2 (Pin 1)
Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the AGP regulator’s pass transistor.
VSEN2 (Pin 10)
Connect this pin to the output of the AGP linear regulator.
The voltage at this pin is regulated to the level
predetermined by the logic-level status of the SELECT pin.
This pin is also monitored for under-voltage events.
SELECT (Pin 11)
This pin determines the output voltage of the AGP bus linear
regulator. A low TTL input sets the output voltage to 1.5V,
while a high input sets the output voltage to 3.3V.
DRIVE3 (Pin 18)
Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the 1.5V regulator’s pass transistor.
VSEN3 (Pin 19)
Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for under-voltage events.
DRIVE4 (Pin 15)
Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the 1.8V regulator’s pass transistor.
VSEN4 (Pin 14)
Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for undervoltage events.
Description
Operation
The HIP6021 monitors and precisely controls 4 output
voltage levels (Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic). It is
designed for microprocessor computer applications with
3.3V, 5V, and 12V bias input from an ATX power supply.
The IC has a synchronous PWM controller and three linear
controllers. The PWM controller (PWM) is designed to
regulate the microprocessor core voltage (V
controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter configuration and
regulates the microprocessor core voltage to a level
programmed by the 5-bit digital-to-analog converter (DAC).
One of the linear controllers is designed to regulate the
advanced graphics port (AGP) bus voltage (V
digitally-programmable level of 1.5V or 3.3V. Selection of
7
OUT1
OUT2
). PWM
) to a
HIP6021
either output voltage is achieved by applying the proper
logic level at the SELECT pin. The remaining two linear
controllers supply the 1.5V GTL bus power (V
the 1.8V memory power (V
designed to employ an external pass transistor.
Initialization
The HIP6021 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage (+12V
(+5V
(+3.3V
equal to +5V
protection). The POR function initiates soft-start operation
after all supply voltages exceed their POR thresholds.
Soft-Start
The POR function initiates the soft-start sequence. Initially,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the soft-start interval). Then an internal
28µA current source charges an external capacitor (C
the SS pin to 4.5V. The PWM error amplifier reference input
(+ terminal) and output (COMP pin) are clamped to a level
proportional to the SS pin voltage. As the SS pin voltage
slews from 1V to 4V, the output clamp allows generation of
PHASE pulses of increasing width that charge the output
capacitor(s). After the output voltage increases to
approximately 70% of the set value, the reference input
clamp slows the output voltage rate-of-rise and provides a
smooth transition to the final set voltage. Additionally, all
linear regulators’ reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method provides a
rapid and controlled output voltage rise.
Figure 3 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier
output voltage reach the valley of the oscillator’s triangle
wave. The oscillator’s triangular wave form is compared to
the clamped error amplifier output voltage. As the SS pin
voltage increases, the pulse-width on the PHASE pin
increases. The interval of increasing pulse-width continues
until each output reaches sufficient voltage to transfer
control to the input reference clamp. If we consider the 2.5V
core output (V
During the interval between T2 and T3, the error amplifier
reference ramps to the final value and the converter
regulates the output a voltage proportional to the SS pin
voltage. At T3 the input clamp voltage exceeds the
reference voltage and the output voltage is in regulation.
The remaining outputs are also programmed to follow the
SS pin voltage. The PGOOD signal toggles ‘high’ when all
output voltage levels have exceeded their under-voltage
levels. See the Soft-Start Interval section under
IN
IN
) on the OCSET pin, and the 3.3V input voltage
) at the VAUX pin. The normal level on OCSET is
IN
OUT1
less a fixed voltage drop (see over-current
IN
) in Figure 3, this time occurs at T2.
) at the VCC pin, the 5V input voltage
OUT4
). All linear controllers are
OUT3
) and
SS
) on