ISL6307CRZ Intersil, ISL6307CRZ Datasheet
ISL6307CRZ
Specifications of ISL6307CRZ
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ISL6307CRZ Summary of contents
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... ISL6307 with any other voltage rail. Dynamic-VID™ technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting. Ordering Information PART NUMBER TEMP. (°C) PACKAGE ISL6307CRZ 7x7 QFN (See Note) (Pb-free) ISL6307IRZ - 7x7 QFN ...
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Pinout 1 VID7 2 VID6 3 VID5 4 VID4 5 VID3 6 VID2 7 VID1 8 VID0 9 VRSEL 10 OFS 11 IOUT 12 DAC 2 ISL6307 ISL6307 (48-PIN QFN) TOP VIEW ...
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ISL6307 Block Diagram VDIFF VR_RDY RGND x1 VSEN OVP SOFT-START +200mV FAULT LOGIC SS OFS OFFSET REF DAC VRSEL VID7 VID6 VID5 VID4 DYNAMIC VID3 VID VID2 D/A VID1 VID0 COMP FB 2V OC2 IOUT IDROOP GND 3 ISL6307 OVP ...
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Typical Application - 6-Phase Buck Converter with R NTC2 EXTERNAL TCOMP COMPENSATION NETWORK FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT ISL6307 VR_RDY VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ISEN4- VID2 ISEN4+ VID1 ...
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Typical Application - 6-Phase Buck Converter with R FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT ISL6307 VR_RDY VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ISEN4- VID2 ISEN4+ VID1 VID0 PWM2 VRSEL ISEN2- OVP ...
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Typical Application - 6-Phase Buck Converter with DCR Sensing and External TCOMP NTC2 EXTERNAL TCOMP COMPENSATION NETWORK FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT ISL6307 VR_RDY VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ...
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Typical Application - 6-Phase Buck Converter with DCR Sensing and Integrated TCOMP FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT ISL6307 VR_RDY VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ISEN4- VID2 ISEN4+ VID1 VID0 ...
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... Operating Conditions Supply Voltage, VCC (5V bias mode, Note +5V ±5% Ambient Temperature (ISL6307CRZ 0°C to 70°C Ambient Temperature (ISL6307IRZ -40°C to 85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...
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... Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA. Unless Otherwise Specified (Continued) PARAMETER PIN-ADJUSTABLE OFFSET Voltage at OFS Pin for ISL6307CRZ Voltage at OFS Pin for ISL6307IRZ OSCILLATORS Accuracy of Switching Frequency Setting Adjustment Range of Switching Frequency (Note 4) Soft-start Ramp Rate (Note 5, 6) Adjustment Range of Soft-start Ramp Rate (Note 4) ...
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Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA. Unless Otherwise Specified (Continued) PARAMETER VR-RDY Reset Voltage Overvoltage Protection Threshold Overvoltage Reset Threshold OVP Output High Voltage OVP Output Low Voltage NOTES: 3. These parts are designed and ...
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... VID™ operations. PWM1, PWM2, PWM3, PWM4, PWM5, PWM6 - Pulse- width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3, PWM4, PWM5 and PWM 6. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation ...
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MOSFET’s R which is the channel current scaled by R VR_RDY - VR_RDY is used as an indication of the end of soft-start with certain delay per Intel VR11 open- drain logic ...
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Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3) combine to form the AC ripple current and the DC load current. The ripple component has three times the ripple frequency of ...
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PWM signal will remain high until the pulse termination signal marks the beginning of the next cycle by triggering the PWM signal low. Current Sampling During the forced off-time following a PWM transition low, the associated channel current sense amplifier ...
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... Channel current balance is achieved by comparing the sampled current of each channel to the average current to make an appropriate adjustment to the PWM duty cycle of each channel. Intersil’s patented current- balance method is illustrated in Figure 7. In the figure, the average current combines with the channel 1 current I ...
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... The output of the error amplifier, V COMP sawtooth waveform to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry which control voltage regulation is illustrated in Figure 8. ...
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TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) VID4 VID3 VID2 VID1 VID0 400mV 200mV 100mV 50mV 25mV 12.5mV ...
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TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) VID4 VID3 VID2 VID1 VID0 400mV 200mV 100mV 50mV 25mV 12.5mV ...
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TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
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TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
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The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. ...
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... It is important that the driver ICs reach their POR level before the ISL6307 becomes enabled. The schematic in Figure 10 demonstrates sequencing the ISL6307 with the ISL66xx family of Intersil MOSFET drivers, which require 12V (EQ. 13) bias. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller ...
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... At the inception of an overvoltage event, all PWM outputs are commanded low instantly (less than 20ns) until the voltage at VDIFF falls below 0.4V. This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level that might cause damage to the load. ...
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... SW At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state within 20ns commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a soft- start ...
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V_IOUT, 200mV/DIV 0A 50A FIGURE 14. VOLTAGE AT IOUT PIN WITH A NTC NETWORK PLACED BETWEEN IOUT TO GROUND WHEN LOAD CURRENT CHANGES Thermal Monitoring (VR_HOT/VR_FAN) There are two thermal signals to indicate the temperature status of the voltage regulator: ...
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TM 0.39*Vcc 0.33*Vcc 0.28*Vcc VR_FAN VR_HOT T1 T2 FIGURE 17. VR_HOTAND VR_FAN SIGNAL VS TM VOLTAGE Based on the NTC temperature characteristics and the desired threshold of VR_HOT signal, the pull-up resistor RTM1 of TM pin is given by: = ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications ...
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Generally speaking, the most economical solutions are those in which each phase handles between 15 and 20A. All surface-mount designs will tend toward the lower ...
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RISEN for the affected phases (see the section entitled Channel-Current Balance). Choose R in ...
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Case 2: ( 2πC ESR 2π 2π -------------------------------------------- C FB 0.75 V 0.75V ------------------------------------------------------------ - ...
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At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage ...
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0.5 I L, 0.75 I L,PP O L,PP 0.2 0 0.2 0.4 0.6 DUTY CYCLE (V O/ FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY ...
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... Align the output inductors and MOSFETs such that spaces between the components are minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...