ISL6236AIRZ Intersil, ISL6236AIRZ Datasheet
ISL6236AIRZ
Specifications of ISL6236AIRZ
Related parts for ISL6236AIRZ
ISL6236AIRZ Summary of contents
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... ISL6236AIRZ ISL6236 AIRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B ISL6236AIRZ-T* ISL6236 AIRZ -40 to +100 32 Ld 5x5 QFN *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Pinout EN LDO LDOREFIN 2 ISL6236A ISL6236A (32 LD 5x5 QFN) TOP VIEW REF 1 TON 2 VCC 3 4 VREF3 5 VIN 6 LDO ...
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... Thermal Resistance (Typical QFN (Notes Operating Temperature Range . . . . . . . . . . . . . . . .-40°C to +100°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp , and REF, V REF3 IN = -40°C to +100°C, unless otherwise noted. Typical values are ...
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Electrical Specifications No load on LDO, OUT1, OUT2, V VEN_LDO = 5V, T PARAMETER Current-Limit Threshold (Positive, Default) Current-Limit Threshold (Positive, Adjustable) Zero-Current Threshold Current-Limit Threshold (Negative, Default) Soft-Start Ramp Time Operating Frequency On-Time Pulse Width Minimum Off-Time Maximum Duty ...
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Electrical Specifications No load on LDO, OUT1, OUT2, V VEN_LDO = 5V, T PARAMETER LDO Output Current LDO Output Current During Switchover to 5V BYP = 5V, V LDO Output Current During Switchover to 3.3V LDO Short-Circuit Current Undervoltage-Lockout Fault ...
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Electrical Specifications No load on LDO, OUT1, OUT2, V VEN_LDO = 5V, T PARAMETER INPUTS AND OUTPUTS FB1 Input Voltage REFIN2 Input Voltage LDOREFIN Input Voltage SKIP Input Voltage TON Input Voltage EN1, EN2 Input Voltage EN LDO Input Voltage ...
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Pin Descriptions PIN NAME REF 2V Reference Output. Bypass to GND with a 0.1µF (min) capacitor. REF can source up to 50µA for external loads. 1 Loading REF degrades FB and output accuracy according to the REF load-regulation error. TON ...
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Pin Descriptions (Continued) PIN NAME GND Analog Ground for both SMPS and LDO. Connect externally to the underside of the exposed pad. 21 PGND Power Ground for SMPS controller. Connect PGND externally to the underside of the exposed pad. 22 ...
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Typical Performance Curves 7V SKIP MODE 12V IN 7V PWM MODE 25V IN 7V ULTRA SKIP MODE 25V IN 12V SKIP MODE 25V IN 12V PWM MODE IN 100 0.001 ...
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Typical Performance Curves 7V SKIP MODE 12V IN 7V PWM MODE 25V IN 7V ULTRA SKIP MODE 25V IN 12V SKIP MODE 25V IN 12V PWM MODE IN 2.5 2.0 1.5 1.0 0.5 0.0 0.001 0.010 0.100 OUTPUT LOAD (A) ...
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Typical Performance Curves 1.518 1.516 1.514 NO LOAD PWM 1.512 1.510 MAX LOAD PWM 1.508 1.506 1.504 INPUT VOLTAGE (V) FIGURE 15 1.5V OUTPUT VOLTAGE REGULATION OUT1 vs V (PWM MODE) IN ...
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Typical Performance Curves 300 250 200 PWM 150 100 ULTRA-SKIP 50 0 0.001 0.010 0.100 OUTPUT LOAD (A) FIGURE 21 1.05V FREQUENCY vs LOAD OUT2 250 PWM 200 150 100 ULTRA-SKIP 50 SKIP 0 0.001 0.010 0.100 OUTPUT ...
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Typical Performance Curves 450 400 350 PWM 300 250 200 150 ULTRA-SKIP 100 50 0 0.001 0.010 0.100 OUTPUT LOAD (A) FIGURE 27 FREQUENCY vs LOAD OUT1 5.04 5.02 BYP = 0V 5.00 4.98 4.96 4.94 4.92 ...
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Typical Performance Curves INPUT VOLTAGE (V) FIGURE 33. PWM NO LOAD INPUT CURRENT vs V (EN = EN2 = EN LDO = VCC) 177.5 177.0 176.5 176.0 ...
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Typical Performance Curves EN1 5V/DIV V 2V/DIV OUT1 IL1 2A/DIV POK1 2V/DIV FIGURE 39. START- (NO LOAD, PWM MODE) OUT1 EN2 5V/DIV V 2V/DIV OUT2 IL2 2A/DIV FIGURE 41. START- 3.3V (NO LOAD, SKIP MODE) ...
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Typical Performance Curves EN1 5V/DIV V 2V/DIV OUT2 POK1 5V/DIV POK2 5V/DIV FIGURE 45. DELAYED START-UP (V OUT1 EN2 = REF) LGATE1 5V/DIV V RIPPLE 50mV/DIV OUT1 IL1 5A/DIV V RIPPLE 50mV/DIV OUT2 FIGURE 47. LOAD TRANSIENT V LGATE1 5V/DIV ...
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Typical Performance Curves V OUT V 0.5V/DIV OUT2 REFIN2 0.5V/DIV LDO RIPPLE 50mV/DIV FIGURE 51. V TRACKING TO REFIN2 OUT2 EN1 5V/DIV V 0.5V/DIV OUT1 POK1 2V/DIV FIGURE 53. START- 1.5V (NO LOAD, SKIP MODE) OUT1 EN1 5V/DIV ...
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Typical Performance Curves EN2 5V/DIV V 0.5V/DIV OUT2 IL2 2A/DIV POK2 2V/DIV FIGURE 57. START- 1.05V (NO LOAD, OUT1 PWM MODE) EN2 5V/DIV V 0.5V/DIV OUT2 V 2V/DIV OUT1 POK2 5V/DIV POK1 5V/DIV FIGURE 59. DELAYED START-UP (V ...
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Typical Performance Curves LGATE1 5V/DIV V RIPPLE 50mV/DIV OUT1 IL1 5A/DIV V OUT2 FIGURE 63. LOAD TRANSIENT V OUT1 Typical Application Circuits The typical application circuits (Figures 66, 67 and 68) generate the 5V/7A, 3.3V/11A, 1.25V/5A, dynamic voltage/10A, 1.5V/5A, 1.05V/5A ...
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SMPS2 can also use REFIN2 to track its output from 0.5V to 2.50V. The ISL6236A contains fault-protection circuits that monitor the main PWM outputs for undervoltage and overvoltage conditions. A power-on sequence block controls the power-up timing of the ...
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VIN: 5.5V TO 25V C 8 1µ 10µF Q3a SI4816BDY OUT1 – PCI 3.3µH 1 1.25V/5A 0.1µF Q3b C 11 330µF 9mΩ 6.3V VCC R 1 7.87kΩ 5V FB1 TIED TO GND = 5V ...
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VIN: 5.5V TO 25V C 8 1µ 10µF SI4816BDY Q3a OUT1 3.3µ 1.5V/5A 0.1µF Q3b C 11 330µF 9mΩ 6.3V VCC 3.3V VCC FB1 TIED TO GND = 5V FB1 TIED TO VCC ...
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VIN: 4.5V TO 5.5V 1µ 10µF SI4816BDY Q3a OUT1 3.3µH 1 1.5V/5A 0.1µF Q3b 330µF 9mΩ 6.3V VCC 3.3V VCC FB1 TIED TO GND = 5V FB1 TIED TO ...
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VIN: 5.5V TO 25V C 10 10µ IRF7807V C C OUT1 4.7µH 1 0.1µF 5V/ IRF7811AV 330µF 9mΩ 6.3V VCC FB1 TIED TO GND = ...
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BOOT1 UGATE1 PHASE1 PVCC SMPS1 LGATE1 SYNCHRONOUS PWM BUCK GND CONTROLLER ILIM1 EN1 SECFB FB1 POK1 OUT1 OUT1 BYP SW THRESHOLD LDO LDO LDOREFIN VIN EN LDO POWER-ON POWER-ON EN1 SEQUENCE SQUENCE CLEAR FAULT CLEAR FAULT LATCH LATCH EN2 FIGURE ...
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ON VIN + + + OUT REFIN2 (SMPS2 VREF + ILIM + COMP SLOPE COMP + + + 5µA VCC + + Σ Â PHASE OUT FB DECODER 0.9V REF FB 1.1V REF 0.7V REF ...
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Automatic Pulse-Skipping Switchover (Idle Mode) In Idle Mode (SKIP = GND), an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero ...
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ZERO-CROSSING Zero-Crossing DETECTION Detection 0A FB<REG.POINT FB<Reg.Point ON-TIME (t ON-TIME ( FIGURE 73. ULTRASONIC CURRENT WAVEFORMS Reference and Linear Regulators (VREF3, REF, LDO and 14V Charge Pump) The 3.3V reference (VREF3) is accurate ...
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For lower power dissipation, the ISL6236A uses the ON-resistance of the synchronous rectifier as the current-sense element. Use the worst-case maximum value for r from the MOSFET data sheet. Add some margin DS(ON) for the rise in r with temperature. ...
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PVCC is 5V • the gate capacitance of the high-side MOSFET GS Boost-Supply Refresh Monitor In pure skip mode, the converter frequency can be very low with little to no output loading. This produces very long ...
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Power-Up Sequencing and On/Off Controls (EN ) EN1 and EN2 control SMPS power-up sequencing. EN1 or EN2 rising above 2.4V enables the respective outputs. EN1 or EN2 falling below 1.6V disables the respective outputs. Connecting EN1 or EN2 to REF ...
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Adjustable-Output Feedback (Dual-Mode FB) Connect FB1 to GND to enable the fixed 5V or tie FB1 to VCC to set the fixed 1.5V output. Connect a resistive voltage-divider at FB1 between OUT1 and GND to adjust the respective output voltage ...
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Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value using Equation OUT_ IN OUT_ L -------------------------------------------------------------------- - = ⋅ ⋅ ⋅ LIR I ...
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Input Capacitor Selection The input capacitors must meet the input-ripple-current (I ) requirement imposed by the switching current. The RMS ISL6236A dual switching regulator operates at different frequencies. This interleaves the current pulses drawn by the two switches and reduces ...
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The drop is ⋅ when the low-side switch conducts The rectifier is a clamp across the synchronous rectifier that catches the negative inductor swing during the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 11/07 5.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 4. 80 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 37 ISL6236A A ...