ISL6312IRZ Intersil, ISL6312IRZ Datasheet - Page 11

• Manufacturer Part Number: ISL6312IRZ
• Description: IC CTRLR PWM 4PHASE BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6312IRZ

• Applications: Controller, Intel VR10, VR11, AMD CPU
• Voltage - Input: 5 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.38 ~ 1.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To understand the reduction of ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel peak-to-peak inductor current.
In Equation 1, V
voltages respectively, L is the single-channel inductor value,
and f
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
I
I
(
C P P
P P
(
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
–
–
S
)
is the switching frequency.
=
)
=
INPUT-CAPACITOR CURRENT, 10A/DIV
(
--------------------------------------------------------- -
V
(
------------------------------------------------------------------- -
V
IN
IN
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
–
L f
–
CHANNEL 1
INPUT CURRENT
10A/DIV
V
⋅
IN
N V
OUT
L f
S
⋅
and V
⋅
⋅
S
V
) V
OUT
CHANNEL 2
INPUT CURRENT
10A/DIV
IN
⋅
⋅
V
OUT
IN
OUT
) V
⋅
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
11
OUT
are the input and output
(EQ. 1)
(EQ. 2)
ISL6312
ISL6312
Active Pulse Positioning (APP) Modulated PWM
Operation
The ISL6312 uses a proprietary Active Pulse Positioning
(APP) modulation scheme to control the internal PWM
signals that command each channel’s driver to turn their
upper and lower MOSFETs on and off. The time interval in
which a PWM signal can occur is generated by an internal
clock, whose cycle time is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. The advantage of Intersil’s proprietary Active Pulse
Positioning (APP) modulator is that the PWM signal has the
ability to turn on at any point during this PWM time interval,
and turn off immediately after the PWM signal has
transitioned high. This is important because is allows the
controller to quickly respond to output voltage drops
associated with current load spikes, while avoiding the ring
back affects associated with other modulation schemes.
The PWM output state is driven by the position of the error
amplifier output signal, V
signal relative to the proprietary modulator ramp waveform
as illustrated in Figure 3. At the beginning of each PWM time
interval, this modified V
internal modulator waveform. As long as the modified
V
voltage, the PWM signal is commanded low. The internal
MOSFET driver detects the low state of the PWM signal and
turns off the upper MOSFET and turns on the lower
synchronous MOSFET. When the modified V
crosses the modulator ramp, the PWM output transitions
high, turning off the synchronous MOSFET and turning on
the upper MOSFET. The PWM signal will remain high until
the modified V
again. When this occurs the PWM signal will transition low
again.
During each PWM time interval the PWM signal can only
transition high once. Once PWM transitions high it can not
transition high again until the beginning of the next PWM
time interval. This prevents the occurrence of double PWM
pulses occurring during a single period.
To further improve the transient response, ISL6312 also
implements Intersil’s proprietary Adaptive Phase Alignment
(APA) technique, which turns on all phases together under
transient events with large step current. With both APP and
APA control, ISL6312 can achieve excellent transient
performance and reduce the demand on the output
capacitors.
Channel-Current Balance
One important benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
COMP
voltage is lower then the modulator waveform
COMP
voltage crosses the modulator ramp
COMP
COMP
signal is compared to the
, minus the current correction
COMP
February 1, 2011
voltage
FN9289.6