ISL6421AER Intersil, ISL6421AER Datasheet - Page 7

• Manufacturer Part Number: ISL6421AER
• Description: IC REG SGL LNB CONTROL 32-QFN
• Manufacturer: Intersil

Specifications of ISL6421AER

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 1
• Voltage - Output: 13 ~ 18 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

900ms. Simultaneously the overload flag (OLF) bit of the
system register is set to HIGH. After this time has elapsed,
the output is resumed for a time T
the device output will be current limited to between 500mA
and 625mA. At the end of T
detected, the protection circuit will cycle again through T
and T
is detected, normal operation is resumed and the OLF bit is
reset to LOW. Typical T
determined by an internal timer. This dynamic operation can
greatly reduce the power dissipation in a short circuit
condition, still ensuring excellent power-on start-up in most
conditions.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up,
when the dynamic protection is chosen. This can be solved
by initiating a power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF bit
goes HIGH when the current clamp limit is reached and
returns LOW when the overload condition is cleared. The
OLF bit will be LOW at the end of initial power-on soft-start.
The static mode limit serves only to limit the peak current
through the switching FET and cannot precisely set an
average current limit. The sense resistor is calculated by the
equation
where I
should be greater that the normal operating peak current.
Thermal Resistance
This IC is protected against overheating. When the junction
temperature exceeds 150°C (typical), the step-up converter
and the linear regulator are shut off and the overtemp flag
(OTF) bit of the SR is set HIGH. Normal operation is
resumed and the OTF bit is reset LOW, when the junction is
cooled down to 130°C (typical).
External Output Voltage Selection
The output voltage can be selected by the I
Additionally, the QFN package offers a pin (SEL18V) for
independent 13V/18V output voltage selection. When using
this pin, the I
R
SC
=
ON
I
PK
-------- -
I
0.4
2
PK
C BITS
. At the end of a full T
13V
13V
is the peak current through the FET. This value
2
C bits should be initialized to 13V status.
ON
TABLE 1.
+ T
ON
SEL18V
7
ON
OFF
High
, if the overload is still
Low
, during which no overload
ON
time is 920ms as
= 20ms. During T
2
C bus.
O/P VOLTAGE
13V
18V
ON
OFF
,
ISL6421A
SDA
I
(Refer to Philips I
Data transmission from the main microprocessor to the
ISL6421A and vice versa takes place through the 2 wires
I
SCL. Both SDA and SCL are bidirectional lines, connected
to a positive supply voltage via a pull up resistor. (Pull up
resistors to positive supply voltage must be externally
connected). When the bus is free, both lines are HIGH. The
output stage of ISL6421A will have an open drain/open
collector in order to perform the wired-AND function. Data on
the I
standard-mode or up to 400kbits/s in the fast-mode. The
level of logic “0” and logic “1” is dependent of associated
value of Vdd as per electrical specification table. One clock
pulse is generated for each data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 1.
SCL
START and STOP Conditions
As shown in the Figure 2, START condition is a HIGH to
LOW transition of the SDA line, while SCL is HIGH. The
STOP condition is a LOW to HIGH transition on the SDA
line, while SCL is HIGH. A STOP condition must be sent
before each START condition.
2
2
SDA
SCL
C bus interfaces, which consists of the two lines SDA and
C Bus Interface for ISL6421A
CONDITION
2
C bus can be transferred up to 100kbits/s in the
START
S
FIGURE 2. START AND STOP WAVEFORMS
DATA VALID
DATA LINE
STABLE
FIGURE 1. DATA VALIDITY
2
C Specification, Rev. 2.1)
ALLOWED
CHANGE
OF DATA
CONDITION
March 9, 2006
STOP
P
FN9167.3