ISL6421AER Intersil, ISL6421AER Datasheet - Page 8

• Manufacturer Part Number: ISL6421AER
• Description: IC REG SGL LNB CONTROL 32-QFN
• Manufacturer: Intersil

Specifications of ISL6421AER

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 1
• Voltage - Output: 13 ~ 18 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

START
SDA
SCL
Byte Format
Every byte put on the SDA line must be 8-bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull the SDA line
down (LOW) during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6421A will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6421A Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
• A start condition (S)
• A chip address byte (MSB on left; the LSB bit determines
• A sequence of data (1 byte + Acknowledge)
• A stop condition (P)
read (1) or write (0) transmission) (the assigned I
address for the ISL6421A is 0001 00XX)
FIGURE 3. ACKNOWLEDGE ON THE I
MSB
1
2
8
8
2
C BUS
ACKNOWLEDGE
FROM SLAVE
2
C slave
9
ISL6421A
System Register Format
All bits reset to 0 at Power-On
Transmitted Data (
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system registers (SR1/SR2)
of the ISL6421A via I
microprocessor as shown below. The spare bits of SR1/SR2
can be used for other functions.
• R, W = Read and Write bit
• R = Read-only bit
SR DCL - ENT LLC VSEL EN OLF
S 0 0 0 1 0 0 0 R/W ACK
0
0
0
0
0
0
0
0
0
0
SR
1
TABLE 5. SYSTEM REGISTER (SR1 AND SR2)
R, W
R, W
SR1
SR2
1
0
X
X
-
X
X
X
X
X
X
X
X
X
X
X
-
TABLE 3. SYSTEM REGISTER 1 (SR1)
TABLE 4. SYSTEM REGISTER 2 (SR2)
CONFIGURATION
R, W
R, W
DCL
TABLE 2. INTERFACE PROTOCOL
X
0
1
X
X
-
X
0
0
0
1
1
X
-
2
R, W
R, W
I
C bus. These will be written by the
2
X
X
C
X
-
0
0
1
0
1
X
bus WRITE mode)
OTF
R, W R, W R, W R, W
R, W R, W R, W
ENT
X
X
1
1
1
1
1
1
1
1
1
0
X SR2 is selected; to read
LLC
-
X
SR1 is selected
Vout1 = 13V,
Vboost1 = 13V + Vdrop
Vout1 = 18V,
Vboost1 = 18V + Vdrop
Vout1 = 14V,
Vboost1 = 14V + Vdrop
Vout1 = 19V,
Vboost1 = 19V + Vdrop
22kHz tone is controlled
by the DSQIN pin input
22kHz tone is ON,
DSQIN pin input is
disabled
Dynamic current limit
NOT selected
Dynamic current limit
selected
PWM and Linear for
channel 1 disabled
Data (8 bits)
OTF flag.
VSEL
X
FUNCTION
FUNCTION
OTF
EN
R
March 9, 2006
ACK P
FN9167.3
OLF
R
R
X