ISL6421AER Intersil, ISL6421AER Datasheet - Page 9

• Manufacturer Part Number: ISL6421AER
• Description: IC REG SGL LNB CONTROL 32-QFN
• Manufacturer: Intersil

Specifications of ISL6421AER

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 1
• Voltage - Output: 13 ~ 18 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Received Data (
The ISL6421A can provide to the master a copy of the
System Register information via the I
The read mode is Master activated by sending the chip
address with R/W bit set to 1. At the following Master
generated clock bits, the ISL6421A issues a byte on the
SDA data bus line (MSB transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
• Not acknowledge, stopping the read mode
While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6421A.
I
NOTE: V
DCL ISEL ENT LLC VSEL EN OTF OLF
These bits are read as they were
after the last write operation.
2
Input Logic High, VIH
Input Logic Low, VIL
Input Logic Current, IIL
SCL Clock Frequency
transmission of another byte from the ISL6421A.
communication.
C Electrical Specifications
DD
TABLE 6. READING SYSTEM REGISTERS
= 5.0V/3.3V.
PARAMETER
I
2
C
Bus Read Mode)
9
0
1
0
1
2
C bus in read mode.
Tj ≤ 130°C, Normal
operation
Tj > 150°C, Power
blocks disabled
Iout < Imax, Normal
operation
Iout > Imax, Overload
protection triggered
FUNCTION
SDA, SCL
SDA, SCL
SDA, SCL; 0.4V < Vin < 4.5V
TABLE 8. I
TEST CONDITION
ISL6421A
2
C SPECIFICATIONS
Power-On I
The I
reset at power-on. The I
Power OK logic signal from the UVLO circuit. This signal will
go HIGH when chip power is OK. As long as this signal is
LOW, the interface will not respond to any I
and the system register SR is initialized to all zeros, thus
keeping the power blocks disabled.
Once Vcc rises above the UVLO level, the POWER OK
signal given to the I
interface becomes operative and the SR can be configured
by the main microprocessor. About 400mV of hysteresis is
provided in the UVLO threshold to avoid false triggering of
the Power-On reset circuit.
(I
as (or later than) all other I
valid).
ADDRESS Pin
Connecting this pin to GND forces the chip I
address to 0001000; applying a voltage >2.7V forces the
address to 0001001, as shown below.
2
C comes up with EN = 0, EN goes HIGH at the same time
“0001000”
“0001001”
2
Vaddr-1
Vaddr-2
C interface built into the ISL6421A is automatically
Vaddr
TABLE 7. ADDRESS PIN CHARACTERISTICS
2
C Interface Reset
2
MINIMUM
C interface block will be HIGH, the I
0
2
2.7V
MIN
0V
C interface block will receive a
2
C data for the PWM becomes
0.7 x V
TYPICAL
0.3 x V
100kHz
TYP
DD
DD
-
-
2
2
C commands
C interface
MAXIMUM
400kHz
March 9, 2006
10µA
MAX
2.0V
5.0V
FN9167.3
2
C