L6726ATR STMicroelectronics, L6726ATR Datasheet - Page 16

• Manufacturer Part Number: L6726ATR
• Description: IC CTRLR PWM SGL PHASE 8-SOIC
• Manufacturer: STMicroelectronics
• Type: Step-Down (Buck)r

Specifications of L6726ATR

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: Adj to 0.8V
• Frequency - Switching: 270kHz
• Voltage - Input: 1.5 ~ 12 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Output Current: 1.5 A
• Input Voltage: 4.1 V to 13.2 V
• Operating Temperature Range: - 40 C to + 150 C
• Mounting Style: SMD/SMT
• For Use With: 497-9046 - BOARD EVAL BASED ON L6726A497-6364 - BOARD DEMO FOR TS4995EIJT497-6259 - BOARD EVAL 1PH STPDN CONV L6726A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-5906-2

Application details
16/35
depending on the output capacitor ESR. The DC gain of the modulator is simply the input
voltage V
V
The compensation network closes the loop joining FB and COMP node with transfer
function ideally equal to -gm
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F
should not exceed F
cross 0 dB axis with -20 dB/decade slope.
As an example,
Figure 9.
●
●
compensation
open loop
closed loop
OUT
open loop
converter
OTA
gain
gain
gain
Open loop converter singularities:
a)
b)
Compensation Network singularities frequencies:
a)
b)
gain
is scaled and transferred to FB node by the output resistor divider.
Gain
[dB]
IN
0dB
F
divided by the peak-to-peak oscillator voltage ΔV
F
LC
F
Example of type II compensation.
F
P
ESR
Z
=
=
Figure 9
=
--------------------------------- -
2π L C
------------------------------------------------- -
2π R
=
------------------------------
2π R
SW
------------------------------------------- -
2π C
⋅
⋅
/2π. To achieve a good phase margin, the control loop gain has to
1
1
⋅
⋅
F
F
F
shows an asymptotic bode plot of a type II compensation.
⋅
Z
⋅
OUT
1
⎛
⎝
OUT
C
-------------------- -
C
C
1
0dB
·
F
F
Z
F
+
Doc ID 12754 Rev 4
F
⋅
⋅
F
) can be fixed choosing the right R
ESR
.
C
LC
C
P
P
⎞
⎠
F
ESR
F
0dB
F
P
OSC
20log (gm·R
20log [V
.
F
; however, for stability, it
IN
Log (Freq)
/ΔV
F
)
OSC
·R
OS
/(R
L6726A
FB
+R
OS
)]