OPTOCOUPLER CMOS 12MBD 8-SOIC

HCPL-0710

Manufacturer Part NumberHCPL-0710
DescriptionOPTOCOUPLER CMOS 12MBD 8-SOIC
ManufacturerAvago Technologies US Inc.
HCPL-0710 datasheet
 


Specifications of HCPL-0710

Voltage - Isolation3750VrmsNumber Of Channels1, Unidirectional
Current - Output / Channel10mAData Rate12.5MBd
Propagation Delay High - Low @ If20nsInput TypeLogic
Output TypePush-Pull, Totem-PoleMounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)No. Of Channels1
Isolation Voltage3.75kVOptocoupler Output TypeGate Drive
Input Current10µAOutput Voltage5V
Opto Case StyleSOICNo. Of Pins8
Propagation Delay Low-high40nsCommon Mode Voltage Vcm1000V
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names516-1116-5
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HCPL-7710/0710
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-7710 or HCPL-0710 optocouplers
utilize the latest CMOS IC technology to achieve outstand-
ing performance with very low power consumption. The
HCPL-x710 require only two bypass capacitors for complete
CMOS compatibility.
Basic building blocks of the HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a CMOS detector IC. A
CMOS logic input signal controls the LED driver IC which
supplies current to the LED. The detector IC incorporates
an integrated photodiode, a high-speed transimped-
ance amplifier, and a voltage comparator with an output
driver.
Functional Diagram
**V
1
DD1
2
V
I
NC*
3
LED1
4
GND
1
SHIELD
* Pin 3 is the anode of the internal LED and must be left
unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected
between pins 1 and 4, and 5 and 8.
TRUTH TABLE
(POSITIVE LOGIC)
**
DD2
V
, INPUT
LED1
V
, OUTPUT
I
O
H
OFF
L
ON
CAUTION: It is advised that normal static precautions be taken in handling and assembly
O
of this component to prevent damage and/or degradation which may be induced by ESD.
2
Features
• +5 V CMOS compatibility
• 8 ns maximum pulse width distortion
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
• 10 kV/µs minimum common mode rejection
• -40°C to 100°C temperature range
• Safety and regulatory approvals
TRUTH TABLE
(POSITIVE LOGIC)
8
V
**
DD2
V
, INPUT
LED1
I
H
Applications
7
NC*
L
• Digital fieldbus isolation: DeviceNet, SDS, Profibus
I
O
• AC plasma display panel level shifting
6
V
O
• Multiplexed data transmission
• Computer peripheral interface
5
GND
2
• Microprocessor system interface
H
L
UL Recognized
3750 V rms for 1 min. per UL 1577
5000 V rms for 1 min. per UL 1577 (for HCPL-7710
option 020)
CSA Component Acceptance Notice #5
IEC/EN/DIN EN 60747-5-2
– V
= 630 Vpeak for HCPL-7710 Option 060
IORM
– V
= 560 Vpeak for HCPL-0710 Option 060
IORM
V
, OUTPUT
O
OFF
H
ON
L

HCPL-0710 Summary of contents

  • Page 1

    ... UL Recognized 3750 V rms for 1 min. per UL 1577 5000 V rms for 1 min. per UL 1577 (for HCPL-7710 option 020) CSA Component Acceptance Notice #5 IEC/EN/DIN EN 60747-5-2 – 630 Vpeak for HCPL-7710 Option 060 IORM – 560 Vpeak for HCPL-0710 Option 060 IORM V , OUTPUT O OFF ...

  • Page 2

    ... DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: HCPL-0710 to order product of Small Outline SO-8 package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘ ...

  • Page 3

    ... TYPE NUMBER A XXXX YYWW 1.19 (0.047) MAX. 1.080 ± 0.320 (0.043 ± 0.013) Package Outline Drawing HCPL-7710 Package with Gull Wing Surface Mount Option 300 9.65 ± 0.25 (0.380 ± 0.010 1.19 (0.047) MAX. 1.080 ± 0.320 (0.043 ± 0.013) 2 ...

  • Page 4

    ... Package Outline Drawing HCPL-0710 Outline Drawing (Small Outline SO-8 Package XXXV 3.937 ± 0.127 YWW (0.155 ± 0.005 PIN ONE 0.406 ± 0.076 (0.016 ± 0.003) * 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 ± ...

  • Page 5

    ... T = 200 ° 150 °C smax smin Note: Non-halide flux should be used. Regulatory Information The HCPL-x710 have been approved by the following organizations: UL Recognized under UL 1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. Insulation and Safety Related Specifications ...

  • Page 6

    ... Solder Reflow Temperature Profile Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltages Logic High Input Voltage Logic Low Input Voltage Input Signal Rise and Fall Times 6 HCPL-7710 HCPL-0710 Symbol Option 060 Option 060 I-IV I-IV I-IV I-III I-III 55/100/21 55/100/21 ...

  • Page 7

    Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are +25° Specifications Parameter Logic Low Input Supply Current [1] Logic High Input Supply Current ...

  • Page 8

    ... Unloaded dynamic power dissipation is calculated as follows Device considered a two-terminal device: pins and 4 shorted together and pins and 8 shorted together accordance with UL1577, each HCPL-0710 is proof tested by applying an insulation test voltage ≥4500 V tion current limit, I ≤5 µA). Each HCPL-7710 is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (leakage detec- ...

  • Page 9

    ... Figure 11. Thermal derating curve, dependence of Safety Limiting Value with case temperature per IEC/EN/DIN EN 60747-5- (C) A Figure 6. Typical fall time vs. temperature. HCPL-0710 fig (pF) I Figure 9. Typical rise time vs. load capacitance. HCPL-0710 fig 9 SURFACE MOUNT SO8 PRODUCT 800 P (mW) S 700 I (mA) S 600 500 400 300 200 (150) 100 100 125 150 175 200 CASE TEMPERATURE - C A ...

  • Page 10

    ... V DD2 GND 0.01 µF TO 0.1 µF from low to high. Similarly, the propagation delay from HCPL-0710 fig 12 high to low (t ) input signal to propagate to the output, causing the PLH output to change from high to low. See Figure 14 CMOS 50 PHL V OH 90% 2.5 V CMOS 10% ...

  • Page 11

    ... PSK CLOCK t PSK Figure 16. Parallel data transmission example. HCPL-0710 fig 15 tocouplers in a parallel application is twice t A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The HCPL-x710 optocouplers offer the advantage of ...

  • Page 12

    ... INTERFACE XXXXXX YYY MOTOR CONTROLLER HCPL-0710 fig 16 These components could include such things as devices with serial ports, parallel ports, RS232 and RS485 type ports. As shown in Figure 18, power from the network is used only for the transceiver and input (network) side of the optocouplers. ...

  • Page 13

    ... The non-isolated regulator supplies the transceiver and the non-isolated (network) half of the two optocouplers. ISOLATED HCPL SWITCHING POWER x710 SUPPLY REG. V+ (SIGNAL) V– (SIGNAL) V+ (POWER) V– (POWER) HCPL-0710 fig 18 GALVANIC ISOLATION BOUNDARY ...

  • Page 14

    ... NETWORK * OPTIONAL FOR BUS V + SENSE POWER SUPPLY Figure 20. Isolated node with transceiver powered by the network. HCPL-0710 fig 19 14 *Bus V+ Sensing It is suggested that the Bus V+ sense block shown in Figure 20 be implemented. A locally powered node with an un-powered isolated Physical Layer will accumulate errors and become bus-off if it attempts to transmit ...

  • Page 15

    ... HCPL-x710 located in the transmit path is eliminat- ed, a RECESSIVE bus state is ensured as the HCPL-x710 output voltage (V AC LINE 5 V REG. ISOLATED SWITCHING HCPL 0710 POWER SUPPLY 5 V REG. HCPL-0710 fig 20 DD1 ) go HIGH. O GALVANIC ISOLATION BOUNDARY V+ (SIGNAL) V– (SIGNAL) V+ (POWER) V– (POWER ...

  • Page 16

    ... Rs REF RXD GND 0.01 µ HCPL-0710 fig 21 PROFIBUS USER: CONTROL STATION (CENTRAL PROCESSING) OR FIELD DEVICE USER INTERFACE PBC OPTICAL ISOLATION MEDIUM Figure 23. PROFIBUS Controller (PBC). HCPL-0710 fig 22 LINEAR OR SWITCHING REGULATOR + + CAN+ 3 SHIELD 2 CAN– 1 V– VREF 0.01 µ ...

  • Page 17

    ... The HCPL-061N offers HCMOS compatibility and the high CMR performance (1 kV/µ essential in industrial communication interfaces. ISO DD1 0. µF 0.01 µF GND ISO DD2 0.01 7 µ GND 5 2 ISO 680 Ω E 0.01 µ GND 5 HCPL-0710 fig 23 = 1000 V) CM ISO SHIELD SN75176B 7 – B GND 0.01 µF ...

  • Page 18

    For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © ...