HIP4080A/81AEVALZ Intersil, HIP4080A/81AEVALZ Datasheet - Page 5

• Manufacturer Part Number: HIP4080A/81AEVALZ
• Description: DEMO BOARD FOR HIP4081A
• Manufacturer: Intersil

Specifications of HIP4080A/81AEVALZ

• Main Purpose: Power Management, H Bridge Driver (Internal FET)
• Utilized Ic / Part: HIP4080A, HIP4081A
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: HIP4080A/81AEVAL; HIP4080A/81AEVAL; Q2670719

Charge Pump Circuits
There are two charge pump circuits in the HIP4080A, one for
each of the two upper logic and driver circuits. Each charge
pump uses a switched capacitor doubler to provide about
30µA to 50µA of gate load current. The sourcing current
charging capability drops off as the floating supply voltage
increases. Eventually the gate voltage approaches the level
set by an internal zener clamp, which prevents the voltage
from exceeding about 15V, the safe gate voltage rating of
most commonly available MOSFETs.
Driver Circuits
Each of the four output drivers are comprised of bipolar high
speed NPN transistors for both sourcing and sinking gate
charge to and from the MOSFET switches. In addition, the
sink driver incorporates a parallel-connected N-channel
MOSFET to enable the gate of the power switch gate-source
voltage to be brought completely to 0V.
The propagation delays through the gate driver sub-circuits
while driving 500pF loads is typically less than 10ns.
Nevertheless, the gate driver design nearly eliminates all
gate driver shoot-through which significantly reduces IC
power dissipation.
Application Considerations
To successfully apply the HIP4080A the designer should
address the following concerns:
• General Bias Supply Design Issues
• Upper Bias Supply Circuit Design
• Bootstrap Bias Supply Circuit Design
General Bias Supply Design Issues
The bias supply design is simple. The designer must first
establish the desired gate voltage for turning on the power
switches. For most power MOSFETs, increasing the gate-
source voltage beyond 10V yields little reduction in switch
drain-source voltage drop.
Overcharging the power switch’s gate-source capacitance
also delays turn-off, increases MOSFET switching losses
and increases the energy to be switched by the gate driver
of the HIP4080A, which increases the dissipation within the
HIP4080A. Overcharging the MOSFET gate-source
capacitance also can lead to “shoot-through” where both
upper and lower MOSFETs in a single bridge leg find
themselves on simultaneously, thereby shorting out the high
voltage DC bus supply. Values close to 12V are optimum for
supplying V
up to 15V.
DD
and V
CC
, although the HIP4080A will operate
5
Application Note 9404
Lower Bias Supply Design
Since most applications use identical MOSFETs for both
upper and lower power switches, the bias supply
requirements with respect to driving the MOSFET gates will
also be identical. In case switching frequencies for driving
upper and lower MOSFETs differ, two sets of calculations
must be done; one for the upper switches and one for the
lower switches. The bias current budget for upper and lower
switches will be the sum of each calculation.
Always keep in mind that the lower bias supply must supply
current to the upper gate drive and logic circuits as well as
the lower gate drive circuits and logic circuits. This is due to
the fact that the low side bias supplies (V
bootstrap capacitors and the charge pumps, which maintain
voltage across the upper power switch’s gate-source
terminals.
Good layout practice and capacitor bypassing technique
avoids transient voltage dips of the bias power supply to the
HIP4080A. Always place a low ESR (equivalent series
resistance) ceramic capacitor adjacent to the IC, connected
between the bias terminals V
terminal, V
0.5µF is usually sufficient.
Minimize the effects of Miller feedback by keeping the
source and gate return leads from the MOSFETs to the
HIP4080A short. This also reduces ringing, by minimizing
the length and the inductance of these connections. Another
way to minimize inductance in the gate charge/discharge
path, in addition to minimizing path length, is to run the
outbound gate lead directly “over” the source return lead.
Sometimes the source return leads can be made into a small
“ground plane” on the back side of the PC board making it
possible to run the outbound gate lead “on top” of the board.
This minimizes the “enclosed area” of the loop, thus
minimizing inductance in this loop. It also adds some
capacitance between gate and source which shunts out
some of the Miller feedback effect.
Upper Bias Supply Circuit Design
Before discussing bootstrap circuit design in detail, it is worth
mentioning that it is possible to operate the HIP4080A
without a bootstrap circuit altogether. Even the bootstrap
capacitor, which functions to supply a reservoir of charge for
rapidly turning on the MOSFETs is optional in some cases.
In situations where very slow turn-on of the MOSFETs is
tolerable, one may consider omitting some or all bootstrap
components. Applications such as driving relays or lamp
loads, where the MOSFETs are switched infrequently and
switching losses are low, may provide opportunities for boot
strapless operation. Generally, loads with a lot of resistance
and inductance are possible candidates.
Operating the HIP4080A without a bootstrap diode and/or
capacitor will severely slow gate turn-on. Without a bootstrap
capacitor, gate current only comes from the internal charge
SS
of the IC. A value in the range of 0.22µF and
CC
and V
DD
CC
and the common
/V
DD
December 11, 2007
) charge the
AN9404.3