HIP4080A/81AEVALZ Intersil, HIP4080A/81AEVALZ Datasheet - Page 8

• Manufacturer Part Number: HIP4080A/81AEVALZ
• Description: DEMO BOARD FOR HIP4081A
• Manufacturer: Intersil

Specifications of HIP4080A/81AEVALZ

• Main Purpose: Power Management, H Bridge Driver (Internal FET)
• Utilized Ic / Part: HIP4080A, HIP4081A
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: HIP4080A/81AEVAL; HIP4080A/81AEVAL; Q2670719

Since the internal charge pump offsets any possible diode
leakage and upper drive circuit bias currents, these sources
of discharge current for the bootstrap capacitor will be
ignored. The bootstrap capacitance required for the example
above can be calculated as shown in Equation 4, using
Equation 2.
Therefore a bootstrap capacitance of 0.033µF will result in
less than a 1.0V droop in the voltage across the bootstrap
capacitor during the turn-on period of either of the upper
MOSFETs. If typical values of gate charge and bootstrap
diode recovered charge are used rather than the maximum
value, the voltage droop on the bootstrap supply will be only
about 0.5V
Power Dissipation and Thermal Design
One way to model the power dissipated in the HIP4080A is
by lumping the losses into static losses and dynamic
(switching) losses. The static losses are due to bias current
losses for the upper and lower sections of the IC and include
the sum of the I
switching. The quiescent current is approximately 9mA.
Therefore with a 12V bias supply, the static power
dissipation in the IC is slightly over 100mW.
The dynamic losses associated with switching the power
MOSFETs are much more significant and can be divided into
the following categories:
•
•
•
In practice, the high voltage level-shifter and charge transfer
losses are small compared to the gate drive charge transfer
losses.
The more significant low voltage gate drive charge transfer
losses are caused by the movement of charge in and out of
the equivalent gate-source capacitor of each of the 4
MOSFETs comprising the H-bridge. The loss is a function of
PWM (switching) frequency, the applied bias voltage, the
equivalent gate-source capacitance and a minute amount of
CMOS gate charge internal to the HIP4080A. The low
voltage charge transfer losses are given by Equation 5.
The high voltage level-shifter power dissipation is much
more difficult to evaluate, although the equation which
defines it is simple as shown in Equation 6. The difficulty
arises from the fact that the level-shift current pulses, I
and I
P SWLO
C BS
Low Voltage Gate Drive (charge transfer)
High Voltage Level-shifter (V-I) Losses
High Voltage Level-shifter (charge transfer)
OFF
=
, are not perfectly in phase with the voltage at the
18nC
---------------------------------------- -
=
f PWM
12.0-11.0
+
CC
12.5nC
×
and I
(
Q G
DD
+
Q IC
currents when the IC is not
8
)
×
V BIAS
Application Note 9404
(EQ. 4)
(EQ. 5)
ON
upper MOSFET source terminals, V
delays within the IC. These time-dependent source voltages
(or “phase” voltages) are further dependent on the gate
capacitance of the driven MOSFETs and the type of load
(resistive, capacitive or inductive) which determines how
rapidly the MOSFETs turn on. For example, the level-shifter
I
upper logic circuits before the phase voltage even moves. As
a result, little level-shift power dissipation may result from the
i
power dissipation associated with it, since the phase voltage
generally remains high throughout the duration of the i
pulse.
Lastly, there is power dissipated within the IC due to charge
transfer in and out of the capacitance between the upper
driver circuits and V
phenomena, it closely resembles the form of Equation 5,
except that the capacitance is much smaller than the
equivalent gate-source capacitances associated with power
MOSFETs. On the other hand, the voltages associated with
the level-shifting function are much higher than the voltage
changes experienced at the gate of the MOSFETs. The
relationship is shown in Equation 7.
The power associated with each of the two high voltage tubs
in the HIP4080A derived from Equation7 is quite small, due
to the extremely small capacitance associated with these
tubs. A “tub” is the isolation area which surrounds and
isolates the high side circuits from the ground referenced
circuits of the IC. The important point for users is that the
power dissipated is linearly related to switching frequency
and the square of the applied bus voltage.
The tub capacitance in Equation 7 varies with applied
voltage, V
shift of the I
voltage, V
the Q
of Equation 5 through Equation 7 to calculate total power
dissipation is at best difficult. The equations do, however,
allow users to understand the significance that MOSFET
choice, switching frequency and bus voltage play in
determining power dissipation. This knowledge can lead to
corrective action when power dissipation becomes
excessive.
Fortunately, there is an easy method which can be used to
measure the components of power dissipation rather than
calculating them, except for the tiny “tub capacitance”
component.
ON
ON
P SHIFT
P TUB
and I
pulse, whereas the I
IC
=
in Equation 5 is not easy to measure. Hence the use
OFF
=
C TUB
SHIFT
SHIFT
-- -
T
ON
I
∫
pulses may come and go and be latched by the
T
O
, making its solution difficult, and the phase
and I
, in Equation 6 are difficult to measure. Even
(
×
I ON t ( )
V SHIFT
2
SS
OFF
. Since it is a charge transfer
+
OFF
pulses with respect to the phase
I OFF t ( ) )
×
f PWM
pulse may have a significant
×
V SHIFT t ( )
SHIFT
due to propagation
×
December 11, 2007
dt
AN9404.3
(EQ. 6)
(EQ. 7)
OFF