ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet
ADC08D1500DEV/NOPB
Specifications of ADC08D1500DEV/NOPB
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ADC08D1500DEV/NOPB Summary of contents
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... T +85°C) temperature range. A Features ■ Internal Sample-and-Hold ■ Single +1.9V ±0.1V Operation Block Diagram © 2009 National Semiconductor Corporation ADC08D1500 ■ Choice of SDR or DDR output clocking ■ Interleave Mode for 2x Sample Rate ■ Multiple ADC Synchronization Capability ■ Guaranteed No Missing Codes ■ ...
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Ordering Information Industrial Temperature Range (-40°C < T ADC08D1500CIYB ADC08D1500DEV Pin Configuration * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. www.national.com < +85°C) A 128-Pin Exposed Pad LQFP Development Board 2 ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit 3 OutV / SCLK OutEdge / DDR / 4 SDATA 15 DCLK_RST CAL 29 PDQ 14 FSR/ECE Description Output Voltage Amplitude and Serial Interface Clock. ...
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Pin Functions Pin No. Symbol CalDly / DES / 127 SCS 18 CLK+ 19 CLK I− Q− CMO ...
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Pin Functions Pin No. Symbol Equivalent Circuit R 32 EXT 34 Tdiode_P 35 Tdiode_N Description External bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See 1.1.1 Self-Calibration. Temperature Diode Positive (Anode) and Negative (Cathode). These pins may be ...
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Pin Functions Pin No. Symbol DI7− / DQ7− DI7+ / DQ7 DI6− / DQ6− DI6+ / DQ6 DI5− / DQ5− DI5+ / ...
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Pin Functions Pin No. Symbol Equivalent Circuit 42, 53, 64, 74, 87, 97, DR GND 108, 119 52, 63, 98, NC 109, 120 Description Ground return for Connection. Make no connection to these pins. 7 www.national.com ...
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... Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage ( Supply Difference Voltage on Any Input Pin (Except Voltage (Maintaining Common Mode) Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) ≤ ...
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Symbol Parameter SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free dynamic Range IMD Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) INTERLEAVE MODE (DES ...
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Symbol Parameter Bandgap Reference Output V BG Voltage Bandgap Reference Voltage Temperature Coefficient Maximum Bandgap Reference C V LOAD BG load Capacitance TEMPERATURE DIODE CHARACTERISTICS ΔV Temperature Diode Voltage BE CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Match Positive Full-Scale Match ...
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Symbol Parameter POWER SUPPLY CHARACTERISTICS I Analog Supply Current A I Output Driver Supply Current DR P Power Consumption D D.C. Power Supply Rejection PSRR1 Ratio A.C. Power Supply Rejection PSRR2 Ratio AC ELECTRICAL CHARACTERISTICS f Maximum Input Clock Frequency ...
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Symbol Parameter Over Range Recovery Time PD low to Rated Accuracy t WU Conversion (Wake-Up Time) DCS f Serial Clock Frequency SCLK t Data to Serial Clock Setup Time (Note 11) SSU t Data to Serial Clock Hold Time SH ...
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Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. Note 14: Each of the two converters ...
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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one- half the sampling frequency, ...
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Timing Diagrams FIGURE 3. ADC08D1500 Timing — SDR Clocking FIGURE 4. ADC08D1500 Timing — DDR Clocking 15 20152114 20152159 www.national.com ...
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FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low www.national.com FIGURE 5. Serial Interface Timing FIGURE 6. Clock Reset Timing in DDR Mode 16 20152119 20152120 20152123 ...
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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High FIGURE 9. Self Calibration and On-Command Calibration Timing 17 20152124 20152125 www.national.com ...
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Typical Performance Characteristics INL vs. CODE DNL vs. CODE POWER CONSUMPTION vs. SAMPLE RATE www.national.com V =V =1.9V, F =1500MHz CLK INL vs. TEMPERATURE 20152164 DNL vs. TEMPERATURE 20152166 ENOB vs. TEMPERATURE 20152181 18 =25°C unless otherwise ...
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ENOB vs. SUPPLY VOLTAGE 20152177 ENOB vs. INPUT FREQUENCY 20152179 SNR vs. SUPPLY VOLTAGE 20152169 ENOB vs. SAMPLE RATE SNR vs. TEMPERATURE SNR vs. SAMPLE RATE 19 20152178 20152168 20152170 www.national.com ...
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SNR vs. INPUT FREQUENCY THD vs. SUPPLY VOLTAGE THD vs. INPUT FREQUENCY www.national.com THD vs. TEMPERATURE 20152171 THD vs. SAMPLE RATE 20152173 SFDR vs. TEMPERATURE 20152175 20 20152172 20152174 20152185 ...
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SFDR vs. SUPPLY VOLTAGE 20152184 SFDR vs. INPUT FREQUENCY 20152183 Spectral Response at FIN = 745 MHz 20152188 SFDR vs. SAMPLE RATE Spectral Response at FIN = 373 MHz CROSSTALK vs. SOURCE FREQUENCY 21 20152182 20152187 20152163 www.national.com ...
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FULL POWER BANDWIDTH www.national.com 20152186 22 ...
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Functional Description The ADC08D1500 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...
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Control Modes Much of the user control can be accomplished with several control pins that are provided. Examples include initiation of the calibration cycle, power down mode and full scale range setting. However, the ADC08D1500 also provides an Extend- ...
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DCLK. See 2.4.3 Output Edge Synchronization. 1.1.5.3 Double Data Rate A choice of single data rate (SDR) or double data rate (DDR) output is offered. With single data rate the output clock (DCLK) frequency ...
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Feature SDR or DDR Clocking DDR Clock Phase SDR Data transitions with rising or falling DCLK edge LVDS output level Power-On Calibration Delay Full-Scale Range Input Offset Adjust Dual Edge Sampling Selection Dual Edge Sampling Input Channel Selection DES Sampling ...
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Each Register access consists of 32 bits, as shown in Figure 5 of the Timing Diagrams. The fixed header pattern is 0000 0000 0001 (eleven zeros followed by a 1). The loading se- quence is such that a "0" is ...
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Bit 8 OE: Output Edge. This bit selects the DCLK edge with which the data words transition in the SDR mode and has the same effect as the OutEdge pin in the normal control mode. When this bit is 1, ...
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DES Enable Addr: Dh (1101b) W only (0x3FFF) D15 D14 D13 D12 D11 D10 DEN ACP Bit 15 DES Enable. Setting this bit to ...
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MULTIPLE ADC SYNCHRONIZATION The ADC08D1500 has the capability to precisely reset its sampling clock input to DCLK output relationship as deter- mined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a system to have their DCLK (and ...
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V output pin. Note that the CMO V output potential will change with temperature. The com- CMO mon mode output of the driving device should track this change. IMPORTANT NOTE: An analog input channel that ...
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Out Of Range (OR) Indication When the conversion result is clipped the Out of Range output is activated such that OR+ goes high and OR- goes low. This output is active as long as accurate data on either or ...
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Power-On Calibration Power-on calibration begins after a time delay following the application of power. This time delay is determined by the setting of CalDly, as described in the Calibration Delay Sec- tion, below. The calibration process will be not ...
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If a calibration of the ADC is required in Auto DES mode, the device must be returned to the Normal Mode of operation before performing a calibration cycle. Once the Calibration has been completed, the device can be returned ...
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If the power is applied to the device without an input clock signal present, the current drawn by the device might be be- low 200 mA. This is because the ADC08D1500 gets reset through clocked logic and its initial state ...
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The solution is to keep the analog cir- cuitry well separated from the digital circuitry. High power digital components should not be located on or near any linear component or power supply trace or plane that services ...
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ADC08D1500 as many high speed amplifiers will have higher distortion than will the ADC08D1500, resulting in over- all system performance degradation. Driving the V pin to change the reference voltage mentioned in 2.1 THE REFERENCE VOLTAGE, the ...
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Physical Dimensions NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. www.national.com inches (millimeters) unless otherwise noted 128-Lead Exposed Pad LQFP Order Number ADC08D1500CIYB NS Package Number VNX128A 38 ...
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Notes 39 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...