ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 8

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

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STATIC CONVERTER CHARACTERISTICS
INL
DNL
V
V
PFSE
NFSE
FS_ADJ
NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS
FPBW
B.E.R.
ENOB
SINAD
OFF
OFF
Symbol
Absolute Maximum Ratings
(Notes 2, 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Converter Electrical Characteristics
The following specifications apply after calibration for V
870mV
Floating, Non-Extended Control Mode, SDR Mode, R
Boldface limits apply for T
Analog Supply Voltage (V
Supply Difference
Voltage on Any Input Pin
(Except V
Voltage on V
(Maintaining Common Mode)
Ground Difference
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at T
ESD Susceptibility (Note 4)
Soldering Temperature, Infrared,
Storage Temperature
_ADJ
to standard plated package only)
V
|GND - DR GND|
Human Body Model
Machine Model
10 seconds, (Note 5), (Applies
DR
P-P
- V
, C
IN
Integral Non-Linearity (Best fit)
Differential Non-Linearity
Resolution with No Missing
Codes
Offset Error
Input Offset Adjustment Range
Positive Full-Scale Error
Negative Full-Scale Error
Full-Scale Adjustment Range
Full Power Bandwidth
Bit Error Rate
Gain Flatness
Effective Number of Bits
Signal-to-Noise Plus Distortion
Ratio
+, V
A
L
IN
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f
+, V
IN
- )
IN
-
Parameter
A
≤
A
85°C
)
A
= T
MIN
to T
−0.15V to (V
MAX
−65°C to +150°C
. All other limits T
-0.15V to 2.5V
0V to 100 mV
0V to 100 mV
DC Coupled, 1MHz Sine Wave
Overranged
DC Coupled, 1MHz Sine Wave
Overranged
Extended Control Mode
(Note 9)
(Note 9)
Extended Control Mode
Normal Mode (non DES)
d.c. to 500 MHz
d.c. to 1 GHz
f
f
f
f
IN
IN
IN
IN
= 373 MHz, V
= 748 MHz, V
= 373 MHz, V
= 748 MHz, V
A
+0.15V)
±25 mA
±50 mA
2500V
235°C
EXT
2.3 W
250V
2.2V
A
= V
= 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential.
Conditions
DR
A
IN
IN
IN
IN
= +1.9V
8
= 25°C, unless otherwise noted. (Notes 6, 7)
= FSR − 0.5 dB
= FSR − 0.5 dB
= FSR − 0.5 dB
= FSR − 0.5 dB
Operating Ratings
Soldering
Semiconductor’s Reflow Temperature Profile specifications.
Refer to www.national.com/packaging.
Ambient Temperature Range
Supply Voltage (V
Driver Supply Voltage (V
Analog Input Common Mode Voltage
V
(Maintaining Common Mode)
Ground Difference
CLK Pins Voltage Range
Differential CLK Amplitude
IN
DC
CLK
+, V
Exposed Pad
(|GND - DR GND|)
, OutV = 1.9V, V
128-Lead
Package
= 1.5 GHz at 0.5V
IN
LQFP
- Voltage Range
process
Package Thermal Resistance
A
)
(Note 8)
Typical
IN
±0.15
−1.31
-0.45
26°C / W
10
±0.3
−0.6
±0.5
±1.0
7.25
46.3
45.4
±45
±20
1.7
7.4
FSR (a.c. coupled) = differential
must
-18
DR
θ
P-P
JA
)
with 50% duty cycle, V
(Notes 1, 2)
comply
(Note 8)
θ
10°C / W
Limits
Package)
JC (Top of
±0.9
±0.6
−1.5
43.9
±25
±25
±15
1.0
7.0
8
−40°C
(100% duty cycle)
0.4V
(10% duty cycle)
with
+1.8V to +2.0V
≤
P-P
V
(Thermal Pad)
Error/Sample
2.8°C / W
0V to 2.15V
T
+1.8V to V
CMO
LSB (max)
LSB (max)
LSB (max)
LSB (min)
0V to 2.5V
mV (max)
mV (max)
θ
Bits (min)
Bits (min)
A
dB (min)
dB (min)
to 2.0V
(Limits)
J-PAD
≤
Units
dBFS
dBFS
0V to V
%FS
GHz
BG
Bits
National
mV
±50mV
+85°C
=
0V
P-P
A
A