ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 36

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

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isolate and remedy. The solution is to keep the analog cir-
cuitry well separated from the digital circuitry.
High power digital components should not be located on or
near any linear component or power supply trace or plane that
services analog or mixed signal components as the resulting
common return current path could cause fluctuation in the
analog input “ground” return of the ADC, causing excessive
noise in the conversion result.
Generally, we assume that analog and digital lines should
cross each other at 90° to avoid getting digital noise into the
analog path. In high frequency systems, however, avoid
crossing analog and digital lines altogether. The input clock
lines should be isolated from ALL other lines, analog AND
digital. The generally accepted 90° crossing should be avoid-
ed as even a little coupling can cause problems at high
frequencies. Best performance at high frequencies is ob-
tained with a straight signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. This is
especially important with the low level drive required of the
ADC08D1500. Any external component (e.g., a filter capaci-
tor) connected between the converter's input and ground
should be connected to a very clean point in the analog
ground plane. All analog circuitry (input amplifiers, filters, etc.)
should be separated from any digital components.
2.8 DYNAMIC PERFORMANCE
The ADC08D1500 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications and avoid
jitter-induced noise, the clock source driving the CLK input
must exhibit low rms jitter. The allowable jitter is a function of
the input frequency and the input signal level, as described in
Section 2.3.
It is good practice to keep the ADC input clock line as short
as possible, to keep it well away from any other signals and
to treat it as a transmission line. Other signals can introduce
jitter into the input clock signal. The clock signal can also in-
troduce noise into the analog path if not isolated from that
path.
Best dynamic performance is obtained when the exposed pad
at the back of the package has a good connection to ground.
This is because this path from the die to ground is a lower
impedance than offered by the package pins.
2.9 USING THE SERIAL INTERFACE
The ADC08D1500 may be operated in the non-extended con-
trol (non-Serial Interface) mode or in the extended control
mode. Table 7 and Table 8 describe the functions of pins 3,
4, 14 and 127 in the non-extended control mode and the ex-
tended control mode, respectively.
2.9.1 Non-Extended Control Mode Operation
Non-extended control mode operation means that the Serial
Interface is not active and all controllable functions are con-
trolled with various pin settings. That is, the full-scale range,
the power on calibration delay, the output voltage and the in-
put coupling (a.c. or d.c.). The non-extended control mode is
used by setting pin 14 high or low, as opposed to letting it float.
indicates the pin functions of the ADC08D1500 in the non-
extended control mode.
36
Pin 3 can be either high or low in the non-extended control
mode. Pin 14 must not be left floating to select this mode. See
1.2 NORMAL/EXTENDED CONTROL for more information.
Pin 4 can be high or low or can be left floating in the non-
extended control mode. In the non-extended control mode,
pin 4 high or low defines the edge at which the output data
transitions. See 2.4.3 Output Edge Synchronization for more
information. If this pin is floating, the output clock (DCLK) is a
DDR (Double Data Rate) clock (see 1.1.5.3 Double Data
Rate) and the output edge synchronization is irrelevant since
data is clocked out on both DCLK edges.
Pin 127 in the non-extended control mode sets the calibration
delay. Pin 127 is not designed to remain floating.
2.10 COMMON APPLICATION PITFALLS
Failure to write all register locations when using extend-
ed control mode. When using the serial interface, all 8 user
registers must be written at least once with the default or de-
sired values before calibration and subsequent use of the
ADC. In addition, the first write to the DES Enable register
(Dh) must load the default value (0x3FFFh). Once all registers
have been written once, other desired settings, including en-
abling DES can be loaded.
Driving the inputs (analog or digital) beyond the power
supply rails. For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the AD-
C08D1500. Such practice may lead to conversion inaccura-
cies and even to device damage.
Incorrect analog input common mode voltage in the d.c.
coupled mode. As discussed in section 1.1.4 The Analog In-
puts and 2.2 THE ANALOG INPUT, the Input common mode
voltage must remain within 50 mV of the V
has a variability with temperature that must also be tracked.
Distortion performance will be degraded if the input common
mode voltage is more than 50 mV from V
Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
TABLE 7. Non-Extended Control Mode Operation
127
Pin
TABLE 8. Extended Control Mode Operation
14
3
4
127
Pin
3
4
CalDly Short CalDly Long
Reduced V
OutEdge =
Reduced
(Pin 14 High or Low)
Low
V
Neg
(Pin 14 Floating)
SCS (Serial Interface Chip Select)
OD
IN
SDATA (Serial Data)
SCLK (Serial Clock)
Normal V
Normal V
OutEdge =
Function
High
Pos
OD
CMO
IN
CMO
Control Mode
.
output , which
Extended
Floating
DDR
DES
n/a