ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 33

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D1500 will function with the CAL pin held
high at power up, but no calibration will be done and perfor-
mance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See
On-Command Calibration Section 2.4.2.2.
The internal power-on calibration circuitry comes up in an un-
known logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
2.4.2.2 On-Command Calibration
To initiate an on-command calibration, bring the CAL pin high
for a minimum of t
low for a minimum of t
CAL pin high upon power up will prevent execution of power-
on calibration until the CAL pin is low for a minimum of
t
another t
begin t
brought high. The CalRun signal should be monitored to de-
termine when the calibration cycle has completed.
The minimum t
are required to ensure that random noise does not cause a
calibration to begin when it is not desired. As mentioned in
1.1.1 Self-Calibration for best performance, a self calibration
should be performed 20 seconds or more after power up and
repeated when the operating temperature changes signifi-
cantly according to the particular system performance re-
quirements. ENOB drops slightly as junction temperature
increases and executing a new self calibration cycle will es-
sentially eliminate the change.
During a Power-On calibration cycle, both the ADC and the
input termination resistor are calibrated. As ENOB changes
slightly with junction temperature, an On-Command calibra-
tion can be executed to bring the performance of the ADC in
line.
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in 1.1.1 Self-Calibration. The calibration delay
values allow the power supply to come up and stabilize before
calibration takes place. With no delay or insufficient delay,
calibration would begin before the power supply is stabilized
at its operating value and result in non-optimal calibration co-
efficients. If the PD pin is high upon power-up, the calibration
delay counter will be disabled until the PD pin is brought low.
Therefore, holding the PD pin high during power up will further
delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling
time of the power supply.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
CAL_L
input clock cycles, then brought high for a minimum of
CAL_H
CAL_H
input clock cycles after the CAL pin is thus
CAL_H
input clock cycles. The calibration cycle will
CAL_H
and t
CAL_L
input clock cycles after it has been
CAL_L
input clock cycles. Holding the
input clock cycle sequences
33
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the rising
edge or the falling edge of the DCLK signal, so that either
edge of that DCLK signal can be used to latch the output data
into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchronized
with (changes with) the rising edge of the DCLK+ (pin 82).
When OutEdge is low, the output data is synchronized with
the falling edge of DCLK+.
At the very high speeds of which the ADC08D1500 is capable,
slight differences in the lengths of the DCLK and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on the
DCLK edge that best suits the application circuit and layout.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
For short LVDS lines and low noise systems, satisfactory per-
formance may be realized with the OutV input low. If the LVDS
lines are long and/or the system in which the ADC08D1500
is used is noisy, it may be necessary to tie the OutV pin high.
2.4.5 Dual Edge Sampling
IMPORTANT NOTE: When using the ADC in Extended Con-
trol Mode, the Configuration Register must only be written
when the DES Enable bit = 0. Writing to the Configuration
Register when the DES Enable bit = 1 can cause the internal
DES clock generation circuitry to stop.
The Dual Edge Sampling (DES) feature causes one of the two
input pairs to be routed to both ADCs. The other input pair is
deactivated. One of the ADCs samples the input signal on one
input clock edge (duty cycle corrected), the other samples the
input signal on the other input clock edge (duty cycle correct-
ed). The result is a 1:4 demultiplexed output with a sample
rate that is twice the input clock frequency.
To use this feature in the non-enhanced control mode, allow
pin 127 to float and the signal at the "I" channel input will be
sampled by both converters. The Calibration Delay will then
only be a short delay.
In the enhanced control mode, either input may be used for
dual edge sampling. See Section 1.1.5.1.
IMPORTANT NOTES:
1) For the Extended Control Mode - When using the Auto-
matic Clock Phase Control feature in dual edge sampling
mode, it is important that the automatic phase control is dis-
abled (set bit 14 of DES Enable register Dh to 0) before the
ADC is powered up. Not doing so may cause the device not
to wake-up from the power down state.
2) For the Non-Extended Control Mode - When the AD-
C08D1500 is powered up and DES mode is required, ensure
that pin 127 (CalDly/DES/SCS) is initially pulled low during or
after the power up sequence. The pin can then be allowed to
float or be tied to V
sure that the part enters the DES mode correctly.
3) The automatic phase control should also be disabled if the
input clock is interrupted or stopped for any reason. This is
also the case if a large abrupt change in the clock frequency
occurs.
A
/ 2 to enter the DES mode. This will en-
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