ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 27

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

Each Register access consists of 32 bits, as shown in Figure
5 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in Table 4.
Refer to the Register Description (Section 1.4) for information
on the data to be written to the registers.
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
IMPORTANT NOTE: The Serial Interface should not be used
when calibrating the ADC. Doing so will impair the perfor-
mance of the device until it is re-calibrated correctly. Pro-
gramming the serial registers will also reduce dynamic
performance of the ADC for the duration of the register access
time.
1.4 REGISTER DESCRIPTION
Eight write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A3 loaded after Fixed Header Pattern, A0 loaded last
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TABLE 4. Register Addresses
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Loading Sequence:
4-Bit Address
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hex
Ah
Bh
Ch
Dh
Eh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Fh
Register Addressed
DES Coarse Adjust
"Q" Ch Full-Scale
"I" Ch Full-Scale
DES Fine Adjust
Voltage Adjust
Voltage Adjust
"Q" Ch Offset
Configuration
"I" Ch Offset
DES Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
27
IMPORTANT: The Configuration Register should not be
written if the DES Enable bit = 1. The DES Enable bit
should first be changed to 0, then the Configuration
Register can be written. Failure to follow this procedure
can cause the internal DES clock generation circuitry to
stop.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Addr: 1h (0001b)
D15
D7
1
1
D14
D6
0
1
Must be set to 1b
Must be set to 0b
Must be set to 1b
DCS: Duty Cycle Stabilizer. When this bit is set
to 1b , a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disabled.
POR State: 1b
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set to
0b, the DCLK edges are time-aligned with the
data bus edges ("0° Phase"). When this bit is
set to 1b, the DCLK edges are placed in the
middle of the data bit-cells ("90° Phase"),
using the one-half speed DCLK shown in
Figure 4 as the phase reference.
POR State: 0b
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Double
Data Rate) mode whereby a data word is
output with each rising and falling edge of
DCLK. When this bit is set to a 1b, data bus
clocking follows the SDR (single data rate)
mode whereby each data word is output with
either the rising or falling edge of DCLK , as
determined by the OutEdge bit.
POR State: 0b
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mV
reduced output amplitude of 510 mV
used.
POR State: 1b
P-P
D13
Configuration Register
D5
1
1
is used. When this bit is set to 0b, the
DCS DCP
D12
D4
1
D11
D3
1
D10
nDE
D2
W only (0xB2FF)
1
OV
D9
D1
1
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OE
P-P
D8
D0
1
is