ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 10

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

Block/Pin Functional Descriptions
Detailed descriptions of each individual block in the functional
block diagram on page 3 are included in this section.
Application information and design considerations for each pin
and/or each block are also included.
• IC Bias Power (VDD, VDDP1, VDDP2)
• IC GNDs (VSS, PGND)
- The IC is powered from a 12V
- VDD supplies power to both the digital and analog circuits
- VDDP1 and VDDP2 are the bias supplies for the upper
- Heavy copper should be attached to these pins for a better
- VSS is the reference ground, the return of VDD, of all
- PGND is the power return, the high-current return path of
- Copper planes should be attached to both pins.
and should be bypassed directly to the VSS pin with an
0.1µF low ESR ceramic capacitor.
drivers and the lower drivers, respectively. They should be
decoupled with ceramic capacitors to the PGND pin.
heat spreading.
control circuits and must be kept away from nodes with
switching noises. It should be connected to the PGND in
only one location as close to the IC as practical. For a
secondary side control system, it should be connected to
the net after the output capacitors, i.e., the output return
pinout(s). For a primary side control system, it should be
connected to the net before the input capacitors, i.e., the
input return pinout(s).
both VDDP1 and VDDP2. It should be connected to the
SOURCE pins of two lower power switches or the
RETURNs of external drivers as close as possible with
heavy copper traces.
CT
RD
CT
RD
I_CT
I_CT
10
VDD -
±
VMAX
10% supply.
VMIN
DEAD TIME (DT)
FIGURE 1. SIMPLIFIED CLOCK GENERATOR CIRCUIT
SET CLOCK
-
+
-
+
OUT
OUT
ISL6551
• Undervoltage Lockout (UVLO)
• Bandgap Reference (BGREF)
• Clock Generator (CT, RD)
R
S
- UVLO establishes an orderly start-up and verifies that VDD
- UVLO limits are not applicable to VDDP1 and VDDP2.
- The reference voltage VREF is generated by a precision
- This pin must be pulled up to VDD with a resistance of
- This pin must also be decoupled with an 0.1µF low ESR
- This free-running oscillator is set by two external
- The switching frequency (Fsw) of the power train is half of
is above the turn-on threshold voltage (VDD
drivers are held low during the lockout. UVLO incorporates
hysteresis VDD
while powering up.
bandgap circuit.
approximately 399kΩ for proper operation. For additional
reference loads (no more than 1mA), this pull-up resistor
should be scaled accordingly.
ceramic capacitor.
components as shown in Figure 1. A capacitor at CT is
charged and discharged with two equal constant current
sources and fed into a window comparator to set the clock
frequency. A resistor at RD sets the clock dead time. RD
and CT should be tied to the VSS pin on their other ends
as close as possible. The corresponding CT for a particular
frequency can be selected from Figure 2.
the clock frequency (Fclock), as shown in Equation 1.
Fsw
Q
Q
Q
=
Fclock
------------------ -
2
CLK
HYS
Q
to prevent multiple startup/shutdowns
DT
ON
DT
). All the
January 3, 2006
CLK
(EQ. 1)
FN9066.5