ISL6532AEVAL1

Manufacturer Part NumberISL6532AEVAL1
DescriptionEVALUATION BOARD 1 ISL6532A
ManufacturerIntersil
ISL6532AEVAL1 datasheets
 


Specifications of ISL6532AEVAL1

Main PurposeSpecial Purpose DC/DC, DDR Memory SupplyOutputs And Type3, Non-Isolated
Voltage - Output1.25V, 1.5V, 2.5VVoltage - Input5V, 12V
Regulator TopologyBuckFrequency - Switching250kHz
Board TypeFully PopulatedUtilized Ic / PartISL6532A
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantCurrent - Output-
Power - Output-  
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Data Sheet
ACPI Regulator/Controller for Dual
Channel DDR Memory Systems
The ISL6532A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply V
with high current during
DDQ
S0/S1 states and standby current during S3 state. During
S0/S1 state, a fully integrated sink-source regulator
generates an accurate (V
/2) high current V
DDQ
without the need for a negative supply. A buffered version of
the V
/2 reference is provided as V
DDQ
REF
controller is also integrated for AGP core voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and standby LDO provide a maximum static
±
regulation tolerance of
2% over line, load, and temperature
ranges. The output is user-adjustable by means of external
resistors down to 0.8V.
Switching memory core output between the PWM regulator
and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the PGOOD signal
indicates V
is within spec and operational.
TT
Each output is monitored for under and overvoltage events.
The switching regulator has overcurrent protection. Thermal
shutdown is integrated.
Ordering Information
TEMP.
PART
PART
RANGE
NUMBER
MARKING
(°C)
,
ISL6532ACR*
**
ISL 6532ACR
0 to +70 28 Ld 6x6 QFN L28.6x6
,
ISL6532ACRZ*
**
ISL6532 ACRZ 0 to +70 28 Ld 6x6 QFN
(Note)
ISL6532AIRZ*
ISL6532 AIRZ -40 to +85 28 Ld 6x6 QFN
(Note)
*Add “-T” suffix for tape and reel.
**Add “-TK” suffix for tape and reel. Please refer to TB347 for details on
reel specifications
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
May 5, 2008
Features
• Generates 3 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference.
- Glitch-free Transitions During State Changes
- LDO Regulator for 1.5V Video and Core voltage
voltage
• Acpi Compliant Sleep State Control
TT
• Integrated V
. An LDO
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs:
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring on All Outputs
• OCP on the Switching Regulator
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-free Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
PKG.
PACKAGE
DWG. #
ACPI compliant PCs
• Graphics Cards - GPU and Memory Supplies
L28.6x6
• ASIC Power Supplies
(Pb-free)
• Embedded Processor and I/O Supplies
L28.6x6
(Pb-free)
• DSP Supplies
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
1-888-INTERSIL or 1-888-468-3774
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6532A
FN9099.5
Buffer
REF
±
2% Over-Temperature

ISL6532AEVAL1 Summary of contents

  • Page 1

    ... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ...

  • Page 2

    Pinout ISL6532A (28 LD QFN) TOP VIEW GNDP 1 5VSBY 2 3 GNDQ GND GNDQ VTT VTT 6 7 VDDQ ISL6532A PGOOD ...

  • Page 3

    Block Diagram P5VSBY VDDQ S3 REGULATOR + - VDDQ(3) VTTSNS VTT REG - VTT(2) + GNDQ DISABLE { R U VREF_IN { GNDA + - UV/OV2 VREF_OUT S3# S5# 5VSBY VOLTAGE REFERENCE 0.800V 0.680V (-15%) 5V ...

  • Page 4

    Simplified Power System Diagram ISL6532A SLP_S3 SLP_S5 5VSBY/3V3SBY V DDQ Q3 V AGP + Typical Application - 5V or 3.3V Input +3.3V PGOOD V DDQ SLP_S3 SLP_S5 V REF VTT_OUT V DDQ Q3 V AGP 1.5V ...

  • Page 5

    Typical Application - Input From 5V Dual +3.3V PGOOD V DDQ SLP_S3 SLP_S5 V REF VTT_OUT V DDQ Q3 V AGP 1. OUT2 5 ISL6532A 5VSBY +12V C BP S3# NCH S5# VREF_OUT OCSET ...

  • Page 6

    ... ISL6532A Thermal Information Thermal Resistance (Typical, Notes 1, 2) QFN Package . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature (Plastic Package +150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp SYMBOL TEST CONDITIONS I S3# and S5# HIGH, UGATE/LGATE Open CC_S0 I ...

  • Page 7

    ... TEST CONDITIONS GATE I GATE I NCH = 0.8V NCH V NCH P5VSBY = 5.0V P5VSBY = 3. VREF_OUT I Periodic load applied with 30% duty cycle VTT_MAX and 10ms period using ISL6532AEVAL1 evaluation board (see Application Note AN1056) Note 3 GBWP Note 3 SR Note VTTSNS/ VDDQ VTTSNS/ VDDQ I OCSET REF ...

  • Page 8

    Functional Pin Description 5VSBY (Pin 2) 5VSBY is the bias supply of the ISL6532A typically connected to the 5V standby rail of an ATX power supply. During S4/S5 sleep states the ISL6532A enters a reduced power mode and ...

  • Page 9

    The calculated capacitance will charge the output SS capacitor bank on the V rail in a controlled manner without TT reaching the current limit of the V LDO. TT NCH (Pin 22) NCH is an open-drain output that ...

  • Page 10

    S3 S5 12VATX 2V/DIV 5VSBY 1V/DIV V AGP 500mV/DIV 2048 CLOCK 2048 CLOCK CYCLES CYCLES SOFT-START SOFT-START ENDS 12V POR INITIATES PGOOD COMPARATOR FIGURE 1. TYPICAL COLD START and the V switching regulator will be disabled. NCH is DDQ pulled ...

  • Page 11

    T1. The output is brought back into regulation by time T2 as long as the overcurrent event has cleared. V DDQ V AGP V TT 500mV/DIV INTERNAL ...

  • Page 12

    Application Guidelines Layout Considerations Layout is very important in high frequency switching converter design. With power devices switching efficiently at 250kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit ...

  • Page 13

    DRIVER OSC PWM COMPARATOR - DRIVER ΔV + OSC E REFERENCE ERROR AMP DETAILED COMPENSATION COMPONENTS COMP ISL6532A REFERENCE ⎛ ⎞ ...

  • Page 14

    ISL6532A 0.8V REFERENCE 650Ω DRIVE2 + - OUTPUT IMPEDANCE C 25 FB2 R 9 ⎛ ⎞ × ⎜ ⎟ 0 ------ - AGP ⎝ ⎠ FIGURE 7. COMPENSATION AND OUTPUT VOLTAGE SELECTION ...

  • Page 15

    Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time ...

  • Page 16

    MOSFET Selection - AGP LDO The main criteria for selection of the linear regulator pass transistor is package selection for efficient removal of heat. Select a package and heatsink that maintains the junction temperature below the rating with a maximum ...

  • Page 17

    ... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...