ISL6523EVAL1 Intersil, ISL6523EVAL1 Datasheet - Page 11

• Manufacturer Part Number: ISL6523EVAL1
• Description: EVALUATION BOARD VRM8.5 ISL6523
• Manufacturer: Intersil

Specifications of ISL6523EVAL1

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 4, Non-Isolated
• Voltage - Output: 1.05 ~ 1.825V, 1.2V, 1.5V, 1.8V
• Current - Output: 14A, 4A, 1A, 1A
• Voltage - Input: 3.3V, 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 200kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6523
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
reference voltage level is the DAC output voltage (DACOUT) for
PWM1. The error amplifier output (V
oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V
The PWM wave is smoothed by the output filter (L
The modulator transfer function is the small-signal transfer
function of V
Gain, given by V
a double pole break frequency at F
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6523) and the impedance networks Z
Z
closed loop transfer function with high 0dB crossing frequency
(f
difference between the closed loop phase at f
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 10. Use these guidelines for locating the poles
and zeros of the compensation network:
FB
0dB
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
OUT
F
∆V
. The goal of the compensation network is to provide a
LC
) and adequate phase margin. Phase margin is the
OSC
) is regulated to the Reference voltage level. The
=
--------------------------------------- -
2π
OUT
×
V
E/A
COMPENSATION DESIGN
OSC
L
1
IN
ERROR
AMP
/V
O
DETAILED COMPENSATION COMPONENTS
ISL6523
×
/V
E/A
C
OSC
COMP
Z
PWM
+
O
COMP
. This function is dominated by a DC
-
FB
-
+
C1
, and shaped by the output filter, with
REFERENCE
C2
DACOUT
+
-
R2
11
DRIVER
DRIVER
Z
F
IN
ESR
LC
E/A
FB
and a zero at F
=
IN
Z
) is compared with the
V
FB
---------------------------------------- -
2π
IN
at the PHASE node.
PHASE
(PARASITIC)
C3
×
0dB
ESR
Z
R1
L
IN
1
O
R3
and 180
O
×
ESR
and C
C
V
C
O
ESR
OUT
O
IN
V
.
o
O
OUT
and
.
)..
ISL6523
Compensation Break Frequency Equations
Figure 11 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 11. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 11 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
PWM2 Controller Feedback Compensation
To reduce the number of external small-signal components
required by a typical application, the standard PWM
controller is internally stabilized. The only stability criteria
that needs to be met relates the minimum value of the output
F
F
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FB
Z1
Z2
100
-20
-40
-60
80
60
40
20
0
and Z
=
=
-----------------------------------
2π R
------------------------------------------------------ -
2π
10
MODULATOR
20
×
×
IN
log
ST
GAIN
(
ND
ST
ND
R1
1
to provide a stable, high bandwidth (BW) overall
2


Zero Below Filter’s Double Pole (~75% F
R2
------- -
R1
100
×
Pole at the ESR Zero
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
F
+
1
C1
Z1


R3
)
F
×
1K
LC
C3
F
FREQUENCY (Hz)
Z2
F
ESR
10K
F
F
F
P1
P2
P1
100K
=
=
F
------------------------------------------------------ -
2π
-----------------------------------
2π
P2
P2
×
×
with the capabilities
R
R
1M
1
2
3
ERROR AMP GAIN
×
×
COMPENSATION
1


C3
OPEN LOOP
C1
--------------------- -
C1
CLOSED LOOP
20
10M
log
GAIN
×
+
C2
C2



GAIN
LC
----------------- -
V
V
P P


)
IN
–


