C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 129

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

12.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
lay
Note: The maximum V
reset before V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic ‘1’. When PORSF
is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
RST
) is typically less than 0.3 ms.
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
DD
DD
ramp time is defined as how fast V
Logic HIGH
Logic LOW
reaches the V
Figure 12.2. Power-On and V
Monitor reset timing. For ramp times less than 1 ms, the power-on reset delay (T
2.70
2.55
2.0
1.0
DD
ramp time is 1 ms; slower ramp times may cause the device to be released from
/RST
RST
V
RST
level.
Power-On
Reset
T
PORDelay
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
DD
DD
ramps from 0 V to V
Monitor Reset Timing
Monitor
Reset
VDD
DD
Monitor is enabled following a
RST
). Figure 12.2. plots the
VDD
DD
t
settles above
DD
ramp time
PORDe-
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