C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 67

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

7.
The Voltage reference MUX on the C8051F360/1/2/6/7/8/9 devices is configurable to use an externally
connected voltage reference, the internal reference voltage generator, or the V
(see Figure 7.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source.
For an external source or the internal reference, REFSL should be set to ‘0’. To use V
source, REFSL should be set to ‘1’.
The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor,
internal oscillators, and Current DAC. This bias is enabled when any of the aforementioned peripherals are
enabled. The bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register
REF0CN; see SFR Definition 7.1 for REF0CN register details. The electrical specifications for the voltage
reference circuit are given in Table 7.1.
The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference
generator and a gain-of-two output buffer amplifier. The internal voltage reference can be driven out on the
VREF pin by setting the REFBE bit in register REF0CN to a ‘1’ (see SFR Definition 7.1). The maximum
load seen by the VREF pin must be less than 200 µA to GND. When using the internal voltage reference,
bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to GND. If the internal refer-
ence is not used, the REFBE bit should be cleared to ‘0’. Electrical specifications for the internal voltage
reference are given in Table 7.1.
Important Note about the VREF Pin: Port pin P0.3 on the C8051F360 device and P0.0 on
C8051F361/2/6/7/89 devices is used as the external VREF input and as an output for the internal VREF.
When using either an external voltage reference or the internal reference circuitry, the port pin should be
configured as an analog pin, and skipped by the Digital Crossbar. To configure the port pin as an analog
pin, set the appropriate bit to ‘0’ in register P0MDIN. To configure the Crossbar to skip the VREF port pin,
set the appropriate bit to ‘1’ in register P0SKIP. Refer to Section “17. Port Input/Output” on page 183 for
Voltage Reference (C8051F360/1/2/6/7/8/9)
VDD
GND
4.7µF
Recommended Bypass
Figure 7.1. Voltage Reference Functional Block Diagram
R1
Capacitors
+
Reference
External
Voltage
Circuit
0.1µF
VREF
VDD
REF0CN
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
0
1
IOSCE
N
Reference
REFBE
Internal
EN
EN
EN
Bias Generator
Temp Sensor
DD
To Analog Mux
(to ADC)
VREF
To ADC, IDAC,
Internal Oscillators
power supply voltage
DD
as the reference
67