C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 48

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

C8051F360/1/2/3/4/5/6/7/8/9
5.1.
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the
positive input: the AMUX0 Port I/O inputs, the on-chip temperature sensor, or the positive power supply
(V
GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode; all other
times, ADC0 operates in Differential Mode. The ADC0 input channels are selected in the AMX0P and
AMX0N registers as described in SFR Definition 5.1 and SFR Definition 5.2.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit
(ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers.
Inputs are measured from ‘0’ to VREF * 1023/1024. Example codes are shown below for both right-justified
and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are measured from -VREF to VREF * 511/512. Example codes are shown below for both right-justi-
fied and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a
Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2,3). See Section “17. Port Input/
Output” on page 183 for more Port I/O configuration details.
48
DD
). Any of the following may be selected as the negative input: the AMUX0 Port I/O inputs, VREF, or
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
–VREF x 256/512
VREF x 511/512
VREF x 256/512
Analog Multiplexer
Input Voltage
Input Voltage
–VREF
0
0
Right-Justified ADC0H:ADC0L
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
(AD0LJST = 0)
0x03FF
0x0200
0x0100
0x0000
0x01FF
0xFF00
0xFE00
0x0100
0x0000
Rev. 1.0
Left-Justified ADC0H:ADC0L
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
(AD0LJST = 1)
0xFFC0
0x8000
0x4000
0x0000
0x7FC0
0xC000
0x4000
0x0000
0x8000