C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 169

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

16. Oscillators
The C8051F36x devices include a programmable internal high-frequency oscillator, a programmable inter-
nal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscillator
can be enabled, disabled, and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 16.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the
OSCLCN register, as shown in SFR Definition 16.3. Both internal oscillators offer a selectable post-scaling
feature. The system clock can be sourced by the external oscillator circuit, either internal oscillator, or the
on-chip phase-locked loop (PLL). The internal oscillator's electrical specifications are given in Table 16.1
on page 171 and Table 16.2 on page 172.
16.1. Programmable Internal High-Frequency (H-F) Oscillator
All devices include a calibrated internal high-frequency oscillator that defaults as the system clock after a
system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR
Definition 16.1. OSCICL is factory calibrated to obtain a 24.5 MHz frequency.
Electrical specifications for the precision internal oscillator are given in Table 16.1 on page 171 and
Table 16.2 on page 172. Note that the system clock may be derived from the programmed internal oscilla-
tor divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8
following a reset.
VDD
Option 2
XTAL2
Option 3
XTAL2
Option 4
Option 1
XTAL2
Figure 16.1. Oscillator Diagram
XTAL1
XTAL2
AGND
AV+
OSCICL
C8051F360/1/2/3/4/5/6/7/8/9
Calibrated Internal
Rev. 1.0
Circuit
Low Frequency
Input
OSCLF
Oscillator
Oscillator
OSCXCN
EN
OSC
EN
OSCICN
OSCLD
n
n
PLL
CLKSEL
OSCLCN
OSCLF OSCLD
000
001
010
100
SYSCLK
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