ATTINY85-20SU Atmel, ATTINY85-20SU Datasheet - Page 38

• Manufacturer Part Number: ATTINY85-20SU
• Description: IC AVR MCU 8K 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY85-20SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.3
7.4.4
7.4.5
7.4.6
7.5
7.5.1
38
Register Description
ATtiny25/45/85
Brown-out Detector
Internal Voltage Reference
Watchdog Timer
Port Pins
MCUCR – MCU Control Register
If the Brown-out Detector is not needed in the application, this module should be turned off. If the
Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes,
and hence, always consume power. In the deeper sleep modes, this will contribute significantly
to the total current consumption. See
able” on page 36
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to
age Reference” on page 44
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
both the I/O clock (clk
will be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an
analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to
“DIDR0 – Digital Input Disable Register 0” on page 125
The MCU Control Register contains control bits for power management.
• Bit 7 – BODS: BOD Sleep
BOD disable functionality is available in some devices, only. See
In order to disable BOD during sleep (see
logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First,
Bit
0x35
Read/Write
Initial Value
“Watchdog Timer” on page 44
CC
BODS
R
7
0
for details on how to configure the Brown-out Detector.
/2 on an input pin can cause significant current even in active mode. Digital
I/O
) and the ADC clock (clk
PUD
R/W
6
0
for details on the start-up time.
CC
“Digital Input Enable and Sleep Modes” on page 59
/2, the input buffer will use excessive power.
R/W
SE
5
0
“Brown-out Detection” on page 43
Table 7-1 on page
SM1
R/W
for details on how to configure the Watchdog Timer.
4
0
ADC
) are stopped, the input buffers of the device
SM0
R/W
3
0
for details.
BODSE
35) the BODS bit must be written to
R
2
0
“Limitations” on page
ISC01
R/W
1
0
and
“Software BOD Dis-
ISC00
R/W
0
0
2586M–AVR–07/10
“Internal Volt-
for details on
37.
MCUCR