ATMEGA16A-MU Atmel, ATMEGA16A-MU Datasheet - Page 243
![MCU AVR 16K FLASH 16MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA16A-MU
Manufacturer Part Number
ATMEGA16A-MU
Description
MCU AVR 16K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16A-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 24-6.
Note:
8154B–AVR–07/09
Signal
Name
MUXEN_3
MUXEN_2
MUXEN_1
MUXEN_0
NEGSEL_2
NEGSEL_1
NEGSEL_0
PASSEN
PRECH
SCTEST
ST
VCCREN
Incorrect setting of the switches in
choices to the S&H circuitry on the negative input of the output comparator in
from either one ADC pin, Bandgap reference source, or Ground.
Boundary-scan Signals for the ADC (Continued)
Direction as Seen
from the ADC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
The AVR ADC is based on the analog circuitry shown in
imation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following:
• The Port Pin for the ADC channel in use must be configured to be an input with pull-up
disabled to avoid signal contention.
Description
Input Mux bit 3
Input Mux bit 2
Input Mux bit 1
Input Mux bit 0
Input Mux for negative input for
differential signal, bit 2
Input Mux for negative input for
differential signal, bit 1
Input Mux for negative input for
differential signal, bit 0
Enable pass-gate of gain stages.
Precharge output latch of
comparator. (Active low)
Switch-cap TEST enable. Output
from x10 gain stage send out to
Port Pin having ADC_4
Output of gain stages will settle
faster if this signal is high first two
ACLK periods after AMPEN goes
high.
Selects Vcc as the ACC reference
voltage.
Figure 24-10
will make signal contention and may damage the part. There are several input
Recommended
Input when Not
in Use
0
0
0
1
0
0
0
1
1
0
0
0
Figure
Figure 24-10
24-10. Make sure only one path is selected
Output Values when Recommended
Inputs are used, and CPU is not
Using the ADC
with a successive approx-
ATmega16A
0
0
0
1
0
0
0
1
1
0
0
0
Table 24-6
should
243
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