PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 129

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 11-3:
 2010 Microchip Technology Inc.
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/
CCP2
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
Pin Name
2:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (Microprocessor, Extended
Microcontroller and Microcontroller with Boot Block modes, 80-pin devices only); default assignment is RC1.
All other pin functions are disabled when ICSP or ICD operations are enabled.
Function
CCP2
PORTB FUNCTIONS
INT0
INT1
INT2
INT3
KBI0
KBI1
KBI2
PGC
KBI3
PGD
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
(1)
Setting
TRIS
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
x
0
1
1
x
x
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PIC18F6310/6410/8310/8410
Type
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
TTL
DIG
TTL
TTL
DIG
TTL
TTL
DIG
TTL
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
LATB<0> data output.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 0 input.
LATB<1> data output.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 1 input.
LATB<2> data output.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 2 input.
LATB<3> data output.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 3 input.
CCP2 compare output and CCP2 PWM output; takes priority over port
data.
CCP2 capture input.
LATB<4> data output.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
LATB<5> data output
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
LATB<6> data output
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
Serial execution (ICSP™) clock input for ICSP and ICD operation.
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
Description
DS39635C-page 129
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