PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 343

IC PIC MCU FLASH 4KX16 64TQFP

PIC18LF6310-I/PT

Manufacturer Part Number
PIC18LF6310-I/PT
Description
IC PIC MCU FLASH 4KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF6310-I/PT

Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
54
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
No. Of Pwm
RoHS Compliant
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF6310-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
SUBFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2
FSR2
Q1
=
=
register ‘f’
Subtract Literal from FSR
SUBFSR f, k
0  k  63
f
FSRf – k  FSRf
None
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified by
‘f’.
1
1
SUBFSR 2, 23h
Read
1110
 [ 0, 1, 2 ]
Q2
03FFh
03DCh
1001
Process
Data
Q3
ffkk
destination
Write to
PIC18F6310/6410/8310/8410
kkkk
Q4
SUBULNK
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Operation
Decode
No
FSR2
PC
FSR2
PC
Q1
=
=
=
=
Operation
register ‘f’
Subtract Literal from FSR2
and Return
SUBULNK k
0  k  63
FSR2 – k  FSR2
(TOS) PC
None
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR2. A RETURN
is then executed by loading the PC
with the TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be though of as a special
case of the SUBFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
1
2
SUBULNK 23h
Read
1110
No
Q2
03FFh
0100h
03DCh
(TOS)
1001
Operation
Process
Data
No
Q3
DS39635C-page 343
11kk
destination
Operation
Write to
kkkk
No
Q4

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