PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 30

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
TABLE 1-3:
DS39635C-page 30
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
V
V
AV
AV
Legend: TTL = TTL compatible input
Note 1:
SS
DD
SS
DD
RJ0
ALE
RJ1
OE
RJ2
WRL
RJ3
WRH
RJ4
BA0
RJ4
CE
RJ6
LB
RJ7
UB
2:
3:
Pin Name
ST = Schmitt Trigger input with CMOS levels
I
P
Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
Default assignment for CCP2 in all operating modes (CCP2MX is set).
Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).
= Input
= Power
PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)
11, 31, 51, 70
12, 32, 48, 71
Pin Number
TQFP
62
61
60
59
39
40
41
42
26
25
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
P
P
P
P
Buffer
Type
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
PORTJ is a bidirectional I/O port.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Digital I/O.
External memory address latch enable.
Digital I/O.
External memory output enable.
Digital I/O.
External memory write low control.
Digital I/O.
External memory write high control.
Digital I/O.
External Memory Byte Address 0 control.
Digital I/O
External memory chip enable control.
Digital I/O.
External memory low byte control.
Digital I/O.
External memory high byte control.
CMOS = CMOS compatible input or output
Analog = Analog input
O
I
2
C = ST with I
= Output
2
C™ or SMB levels
Description
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