PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 295

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.5
The overall structure of the code protection on the
PIC18F6310/6410/8310/8410 Flash devices differs
from previous PIC18 devices.
For all devices in the PIC18FX310/X410 family, the
user program memory is made of a single block.
Figure 24-5
for individual devices. Code protection for this block is
controlled by a single bit, CP (CONFIG5L<0>). The CP
bit inhibits external reads and writes; it has no direct
effect in normal execution mode.
24.5.1
The program memory may be read to any location
using the table read instructions. The Device ID and the
Configuration registers may be read with the table read
instructions.
For devices with the external memory interface, it is
possible to execute a table read from an external
program memory space and read the contents of the
on-chip memory. An additional code protection bit,
FIGURE 24-5:
TABLE 24-3:
 2010 Microchip Technology Inc.
300008h
30000Ch
Legend: Shaded cells are unimplemented.
(PIC18F6310/8310)
File Name
*
Program memory
Program Verification and
Code Protection
Unimplemented
Unimplemented in PIC18F6310/8310 devices; maintain this bit set.
CODE PROTECTION FROM
EXTERNAL TABLE READS
shows the program memory organization
8 Kbytes
Read ‘0’s
Block
CONFIG5L
CONFIG7L*
SUMMARY OF CODE PROTECTION REGISTERS
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F6310/6410/8310/8410
MEMORY SIZE/DEVICE
000000h
001FFFh
002000h
1FFFFFh
Address
Range
Bit 7
—
—
(PIC18F6410/8410)
Bit 6
Program memory
Unimplemented
—
—
PIC18F6310/6410/8310/8410
16 Kbytes
Read ‘0’s
Block
Bit 5
—
—
000000h
003FFFh
004000h
1FFFFFh
Address
EBTR (CONFIG7L<0>), is used to protect the on-chip
program memory space from this possibility. Setting
EBTR prevents table read commands from executing
on any address in the on-chip program memory space.
EBTR is implemented only on devices with the external
memory interface. Its operation also depends on the
particular mode of operation selected. In Extended
Microcontroller mode, programming EBTR enables
protection from external table reads for the entire
program memory. In Microcontroller with Boot Block
mode, only the first 2 Kbytes of on-chip memory (000h
to 7FFh) are protected. This is because, only this range
of internal program memory is accessible by the
microcontroller in this operating mode.
When the device is in Micrcontroller or Microprocessor
modes, EBTR has no effect on code protection.
24.5.2
The Configuration registers can only be written via
ICSP using an external programmer. No separate
protection bit is associated with them.
Range
Bit 4
—
—
CONFIGURATION REGISTER
PROTECTION
Bit 3
(Unimplemented Memory Space)
—
—
Block Code Protection
Controlled By:
Bit 2
CP, EBTR
—
—
Bit 1
DS39635C-page 295
—
—
EBTR
Bit 0
CP