PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 287

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 24-6:
REGISTER 24-7:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed bit
bit 7
bit 6
bit 5-1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed bit
bit 7-1
bit 0
DEBUG
R/P-1
U-0
—
DEBUG: Background Debugger Enable bit
1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose I/O pins
0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode)
Unimplemented: Read as ‘0
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause a Reset
0 = Stack full/underflow will not cause a Reset
Unimplemented: Read as ‘0
CP: Code Protection bit
1 = Program memory block is not code-protected
0 = Program memory block is code-protected
XINST
R/P-0
U-0
—
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
C = Clearable bit
C = Clearable bit
U-0
U-0
—
—
PIC18F6310/6410/8310/8410
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U-0
U-0
—
—
U-0
U-0
—
—
U-0
U-0
—
—
DS39635C-page 287
STVREN
R/P-1
R/C-1
CP
bit 0
bit 0