PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 241
PIC18LF6310-I/PT
Manufacturer Part Number
PIC18LF6310-I/PT
Description
IC PIC MCU FLASH 4KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F6310-IPT.pdf
(412 pages)
2.PIC18F6310-IPT.pdf
(16 pages)
3.PIC18F6310-IPT.pdf
(4 pages)
4.PIC18F6310-IPT.pdf
(28 pages)
5.PIC18F6310-IPT.pdf
(6 pages)
6.PIC18F6310-IPT.pdf
(4 pages)
7.PIC18F8410-IPT.pdf
(404 pages)
Specifications of PIC18LF6310-I/PT
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
54
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
No. Of Pwm
RoHS Compliant
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6310-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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19.0
The Addressable Universal Synchronous Asynchro-
nous Receiver Transmitter (AUSART) module is very
similar in function to the Enhanced USART module,
discussed in the previous chapter. It is provided as an
additional channel for serial communication with
external devices, for those situations that do not require
Auto-Baud Detection (ABD) or LIN/J2602 bus support.
The AUSART can be configured in the following
modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
2010 Microchip Technology Inc.
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
PIC18F6310/6410/8310/8410
The pins of the AUSART module are multiplexed with
the
RG2/RX2/DT2, respectively). In order to configure
these pins as an AUSART:
• SPEN bit (RCSTA2<7>) must be set (= 1)
• TRISG<2> bit must be set (= 1)
• TRISG<1> bit must be cleared (= 0) for
• TRISG<1> bit must be set (= 1) for Synchronous
The operation of the Addressable USART module is
controlled through two
RXSTA2. These are detailed in
Register 19-2
Asynchronous and Synchronous Master modes
Slave mode
Note:
functions
The USART control will automatically
reconfigure the pin from input to output as
needed.
respectively.
of
PORTG
registers:
(RG1/TX2/CK2
DS39635C-page 241
Register 19-1
TXSTA2
and
and
and
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