T89C5121-ICUIL Atmel, T89C5121-ICUIL Datasheet - Page 68

• Manufacturer Part Number: T89C5121-ICUIL
• Description: IC 8051 MCU W/SMART CARD 24SSOP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of T89C5121-ICUIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: Flash RAM
• Eeprom Size: 16K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 5.4 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: Q1468934; T89C5121-ICSIL; T89C5121-ICSIL

Configuration Bits
68
A/T8xC5121
The only mean to remove the security level 2 is to send a Full Chip Erase command.
Table 48. Synthesis of Security Mechanisms
The Bootloader tests that TWI components are connected as slave components on the
TWI external bus and later in the algorithm if characters are received on the UART input.
This default configuration can be changed, after a first programming, in order:
This can be configured with the two higher bits of the SSB Byte detailed in the previous
paragraph.
The bit 7 is used to bypass (if 0) the External TWI Acknowledge test.
The bit 6 is used to bypass (if 0) the UART receipt test.
These two bypass modes can be disabled if a level 0 is applied on, respectively, P3.5
and P3.6 pins. This allows to force and use ISP even if the device has been configured
as programmed device.
Internal
EEPROM
Internal
EEPROM
CRAM
CRAM
Source
–
–
to disable new programming in download mode from external serial
EEPROM to disable ISP programming using UART and
to avoid any conflict with the target hardware on external TWI bus or UART.
Write
Read
Write
Read
Function Protection
The first protection level of the SSB Byte IN the internal EEPROM protects
against ISP Write command
The second protection level of the SSB Byte IN the internal EEPROM protects
against ISP Read commands
The first protection level of the SSB Byte IN the internal EEPROM protects
against ISP Write command in CRAM
The second protection level of the SSB Byte IN the CRAM protects against ISP
Read commands
Data Bytes
Address
3FFD
SSB
4164G–SCR–07/06